DE1-SoC HPS DDR3 Controller with UniPHY fitter error

[Altera_Forum]

Hello, 

 I'm trying to access the HPS DDR3 directly from the FPGA on the DE1-SoC board but I have some fitter issues. In order to access the memory I used SoCKit vip demo as the reference as the DDR3 memory is used there. In the DE1-SoC vip demo reference design in QSys I changed the memory from sdram controller to DDR3 SDRAM controller with UniPHY. I mapped the pin locations for the DDR3 memory in the Assignments Editor according to DE1-SoC user manual. I also set I/O Standard as it is in the documentation. I also wired the controller and hps exported conduits in the quartus verilog design just as it is done in the SoCKit demo. The only problem is I get errors during fitting:  Error (14566): Could not place 31 periphery component(s) due to conflicts with existing constraints (31 pin(s)) Error (175020): Illegal constraint of pin to the region (89, 69) to (89, 80): no valid locations in region Info (14596): Information about the failing component(s): Info (175028): The pin name(s): HPS_DDR3_RZQ Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error (184016): There were not enough single-ended input pin locations available (1 location affected) Info (175029): D27 Info (175015): The I/O pad HPS_DDR3_RZQ is constrained to the location PIN_D27 due to: User Location Constraints (PIN_D27) Info (14709): The constrained I/O pad is contained within this pin Error (175020): Illegal constraint of pin to the region (89, 69) to (89, 80): no valid locations in region Info (14596): Information about the failing component(s): Info (175028): The pin name(s): HPS_DDR3_ADDR Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error (184016): There were not enough single-ended output pin locations available (1 location affected) Info (175029): F26 Info (175015): The I/O pad HPS_DDR3_ADDR is constrained to the location PIN_F26 due to: User Location Constraints (PIN_F26) Info (14709): The constrained I/O pad is contained within this pin  These go for all HPS_DDR3 pins in the design. Right now I don't have a clue what may be the cause of this error. I'm using Quartus 15.0, I know the demos were compiled for Quartus 13, but is there a difference that may cause such errors? I also run the .tcl scripts for pin assignments but it didn't help. Any ideas would be much appreciated.  Best regards

[Altera_Forum]

--- Quote Start ---  Hello,  I'm trying to access the HPS DDR3 directly from the FPGA on the DE1-SoC board but I have some fitter issues. In order to access the memory I used SoCKit vip demo as the reference as the DDR3 memory is used there. In the DE1-SoC vip demo reference design in QSys I changed the memory from sdram controller to DDR3 SDRAM controller with UniPHY. I mapped the pin locations for the DDR3 memory in the Assignments Editor according to DE1-SoC user manual. I also set I/O Standard as it is in the documentation. I also wired the controller and hps exported conduits in the quartus verilog design just as it is done in the SoCKit demo. The only problem is I get errors during fitting:  Error (14566): Could not place 31 periphery component(s) due to conflicts with existing constraints (31 pin(s)) Error (175020): Illegal constraint of pin to the region (89, 69) to (89, 80): no valid locations in region Info (14596): Information about the failing component(s): Info (175028): The pin name(s): HPS_DDR3_RZQ Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error (184016): There were not enough single-ended input pin locations available (1 location affected) Info (175029): D27 Info (175015): The I/O pad HPS_DDR3_RZQ is constrained to the location PIN_D27 due to: User Location Constraints (PIN_D27) Info (14709): The constrained I/O pad is contained within this pin Error (175020): Illegal constraint of pin to the region (89, 69) to (89, 80): no valid locations in region Info (14596): Information about the failing component(s): Info (175028): The pin name(s): HPS_DDR3_ADDR Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error (184016): There were not enough single-ended output pin locations available (1 location affected) Info (175029): F26 Info (175015): The I/O pad HPS_DDR3_ADDR is constrained to the location PIN_F26 due to: User Location Constraints (PIN_F26) Info (14709): The constrained I/O pad is contained within this pin  These go for all HPS_DDR3 pins in the design. Right now I don't have a clue what may be the cause of this error. I'm using Quartus 15.0, I know the demos were compiled for Quartus 13, but is there a difference that may cause such errors? I also run the .tcl scripts for pin assignments but it didn't help. Any ideas would be much appreciated.  Best regards  --- Quote End ---    Hi,  Hope it is not to late to answer your question. DE1-SoC is different from SoC Kit. DE1-SoC has DDR3 that is attached to the HPS and SDRAM that is connected to the FPGA, while the SoCKit has DDR3 on both HPS and the FPGA. This is the reason why the SoCKit design uses the UniPHY DDR3 IP, while the DE1-SoC design uses the SDRAM controller IP.  For DE1-SoC, you cannot use the UniPHY DDR3 IP for the DDR3 that is connected to the HPS. Instead, the settings are done in the HPS Component IP within Qsys (SDRAM tab). Once you've generated the Qsys, remember to run the tcl file “hps_sdram_p0_pin_assignments.tcl” located at <Quartus project directory>\<Qsys file name>\synthesis\submodule.  Running the tcl file will set all the necessary IO standards and termination for the HPS DDR3. You don't have to do any pin location assignment as it is fixed.   Hope it helps...