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Altera_Forum
Honored Contributor I
1,135 Views

MAX10 Compilation Report

This is a Compilation Repor 

Flow Status Successful - Tue Feb 28 14:26:56 2017 Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition Revision Name ACM Top-level Entity Name ACM Family MAX 10 Device 10M50SAE144I7G Timing Models Final Total logic elements 32 / 49,760 ( < 1 % ) 

Total registers 26 Total pins 11 / 101 ( 11 % ) Total virtual pins 0 Total memory bits 0 / 1,677,312 ( 0 % ) Embedded Multiplier 9-bit elements 0 / 288 ( 0 % ) Total PLLs 0 / 1 ( 0 % ) 

UFM blocks 0 / 1 ( 0 % ) ADC blocks 0 / 1 ( 0 % ) 

 

 

Total logic elements -32 ??? 

Total registers 26 ??? 

When I look at RTL Viewer i see thouthands muxes, flip-flops, logic gates - and <1% ???
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9 Replies
Altera_Forum
Honored Contributor I
87 Views

 

--- Quote Start ---  

This is a Compilation Repor 

Flow Status Successful - Tue Feb 28 14:26:56 2017 

Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition 

Revision Name ACM 

Top-level Entity Name ACM 

Family MAX 10 

Device 10M50SAE144I7G 

Timing Models Final 

Total logic elements 32 / 49,760 ( < 1 % ) 

 

Total registers 26 

Total pins 11 / 101 ( 11 % ) 

Total virtual pins 0 

Total memory bits 0 / 1,677,312 ( 0 % ) 

Embedded Multiplier 9-bit elements 0 / 288 ( 0 % ) 

Total PLLs 0 / 1 ( 0 % ) 

 

UFM blocks 0 / 1 ( 0 % ) 

ADC blocks 0 / 1 ( 0 % ) 

 

 

 

Total logic elements -32 ??? 

Total registers 26 ??? 

When I look at RTL Viewer i see thouthands muxes, flip-flops, logic gates - and <1% ??? 

--- Quote End ---  

 

 

possibly plenty of logic optimised away if not driving outputs and RTL is not telling the truth or just your lucky day
Altera_Forum
Honored Contributor I
87 Views

No way for such optimization. I have a lot of code written. It can not be < 1%. I suspect something in Quartus 16.1. I worked before with Quartus II 11.1 - no such things.

Altera_Forum
Honored Contributor I
87 Views

 

--- Quote Start ---  

No way for such optimization. I have a lot of code written. It can not be < 1%. I suspect something in Quartus 16.1. I worked before with Quartus II 11.1 - no such things. 

--- Quote End ---  

 

 

16.1 does silly things. Try close quartus, delete project database and then open project and clean project from project menu.
Altera_Forum
Honored Contributor I
87 Views

OK. Thank you.

Altera_Forum
Honored Contributor I
87 Views

You should be looking at the post-fit Technology Map Viewer, not the RTL Viewer, to get an accurate representation of actual resources selected by the Fitter for use by your design.

Altera_Forum
Honored Contributor I
87 Views

 

--- Quote Start ---  

You should be looking at the post-fit Technology Map Viewer, not the RTL Viewer, to get an accurate representation of actual resources selected by the Fitter for use by your design. 

--- Quote End ---  

 

What difference does it make what viewer I use? This is not logical - Total logic elements 32 / 49,760 ( < 1 % ) for a WHOLE BIG project. 32 elements? really?
Altera_Forum
Honored Contributor I
87 Views

You may have 'a lot' of code, but is it all used/necessary? Have you connected it up correctly? Do your output pins depend on all of it? 

 

If you have a large chunk of code that doesn't contribute to working out what your output pins should be doing, Quartus will optimise it away. Why put it in if nothing is dependant on it? 

 

I'd suggest that the state of whatever output pins you have can be determined by 32 logic elements... 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
87 Views

 

--- Quote Start ---  

You may have 'a lot' of code, but is it all used/necessary? Have you connected it up correctly? Do your output pins depend on all of it? 

 

If you have a large chunk of code that doesn't contribute to working out what your output pins should be doing, Quartus will optimise it away. Why put it in if nothing is dependant on it? 

 

I'd suggest that the state of whatever output pins you have can be determined by 32 logic elements... 

 

Cheers, 

Alex 

--- Quote End ---  

 

Actually my top entity pins are not populated yet. But I have 4 components with connected signals between it. I should try to connect the final stage out.
Altera_Forum
Honored Contributor I
87 Views

 

--- Quote Start ---  

Actually my top entity pins are not populated yet. 

--- Quote End ---  

 

You should have mentioned this earlier. It makes the previous discussion pointless. 

 

Any logic that doesn't affect an output pin or a JTAG test function directly or indirectly will be discarded. Also any logic that doesn't change state because it misses the clock connection or is hold permanently in reset. The behavior is not specific to Quartus 16 or MAX10.
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