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Valued Contributor III
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MAX10 Dual Purpose/JTAG issues

I am using an M08 device and trying to set up dual mode pins. I enabled JTAG pin sharing and disabled nCONFIG, nSTATUS... 

 

I only needed two pins for my user mode (TCK and TMS), but I also added TDI and TDO to the port list and assigned them as std_logic (they are not connected to any signals in the code). This is because according to the config document, all JTAG pins must be assigned as single-ended IO. 

 

On the board there are 10k pull-ups on TMS, JTAGEN, TDO, and TDI (and nSTATUS, CONFIG, and CONFIG_DONE), and 10k pull-down on TCK. 

 

When I try to program the device with a .sof file, the programmer initially recognizes the part, but as soon as I click "Start" I get a "Failed" message and the tool no longer recognizes the device. When I cycle power (re-loading the old, non dual use code), the JTAG recognizes the device again.  

 

What have I done wrong or missed? Is there a good way to prevent use of the JTAG pins in user mode when I want to re-program? 

 

Additional Question: I just saw that in the Device and Pin Options window, under Dual Use Pins, it says "n/a in Internal Configuration". Does this mean I cannot use dual-use with internal configuration? Or just that I cannot use that window when Internal Configuration is set. I did not see anything about this in the Config user Guide. 

 

 

Thanks 

 

Bret
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Valued Contributor III
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This doesn't sound right to me. Everything you describe sounds appropriate. I don't think you're suffering from anything dual-purpose pin related. If JTAGEN is high then, regardless of the JTAG pin sharing setting, you should be able to access the device via JTAG. 

 

Can you confirm that the JTAGEN pin is indeed high? Can you measure it? I appreciate you have a pull-up but I think something untoward is going on. 

 

 

--- Quote Start ---  

When I cycle power (re-loading the old, non dual use code), the JTAG recognizes the device again 

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So you have something programmed into the CFM - right? Can you erase the FPGA's internal memory and work with a blank device? 

 

I'm concerned that the design in CFM is causing the problem, perhaps with the power rails. If a rail is dipping, due to excessive load, then the JTAG is likely to break. 

 

Cheers, 

Alex
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