MAX10: JTAG Instruction Set - Understanding what USBBlaster is doing - later ISP

[Altera_Forum]

I want to do In-System-Programming for the MAX10 over JTAG. 

 As pre-work I would like to understand what the USBBlaster is doing when using the Quartus Programmer to load a .pof-File onto the MAX10. This functionality should be replaced later to do the programming by a microcontroller.  When sniffing the JTAG communication I found some probably undocumented JTAG Instruction Codes. I found some like IDCODE 00 0000 0110 or ISC_ADDRESS_SHIFT 10 0000 0011 in the handbook, but could not find anything about: 00 0000 0010 00 0000 0100 00 0000 0011  What do they stand for?  Do I need to know their meaning for being able to do ISP?

[Altera_Forum]

The USB-Blaster (I suspect you've worked out) is a JTAG host controlled over USB from it's host - e.g. a PC. It simply generates the appropriate JTAG commands fed to it from it's host. 

 As for what JTAG commands the Quartus programmer has it generate - this is not (completely) documented. You've clearly found a few...  JTAG is not really intended to be used in this way. Nor is MAX10 really intended for in-system programming in this way. That's not to say it can't be done - it can.  There are FPGA families that are intended to be programmed from a micro (or similar) - e.g. Cyclone. These devices lend themselves very well to this. However, they don't do this using JTAG.  So, why MAX10? And why are you looking to solve this with JTAG hosted from a micro?  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  So, why MAX10? And why are you looking to solve this with JTAG hosted from a micro?  --- Quote End ---   Thanks Alex.   Why MAX10? It fits our application and we like the internal flash.   Why JTAG? We want to make use of chaining. Multiple MAX10 may be connected to one micro (without wasting pins). We don't care too much about programming performance, but need a way for occasional updates (without having to disassemble the machine, pluggin in additional hardware, running special software, ...)   The handbook says:   --- Quote Start ---  You can program the internal flash including the CFM of MAX 10 devices with ISP through industry standard JTAG interface.    --- Quote End ---  And there is a general flow of how to do, without details. Unfortunately I don't find much more.   Is there a (complete) documentation how ISP for MAX10 via JTAG can be achieved? Or how the Quartus Programmer works?   Why is MAX10 NOT intended to do so?

[Altera_Forum]

JTAG programming of FPGAs came about as an extension of boundary scan testing, a facility to aid manufacturers to determine if boards have been assembled correctly. Extending JTAG to do this programming allowed manufacturers to both test and program boards in one step. As such, JTAG is primarily intended for use in manufacturing test and during development. 

 The main reasons not to use JTAG as you intend is because it's not completely documented by Altera and it's not intended to be used in that way.  If you are intending to host your system from a micro, then there are facilities in other FPGA families specifically designed for this. Cyclone (the family I think you should be considering), Arria & Stratix all support Passive Serial programming. This is a low pin count (as low as 4) programming method that allows daisy chaining of parts. Look at that 'PS Configuration' section of "chapter 8. configuration and remote system upgrades in cyclone iv devices (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf)". Specifically figure 8-14. You don't necessarily need to source the data directly from the external memory, this can come from your micro.    --- Quote Start ---  we like the internal flash  --- Quote End ---  Solely for programming? If so, I suggest you boot your Cyclone IV FPGA directly from the micro. Thus removing the need for it.  If you want non-volatile for other purposes the strap a $0.50 serial FLASH device to your FPGA. You could (although I suggest you don't) chose to boot your FPGA from this FLASH, connected in an Active Serial configuration - see the same configuration guide above. You'd then connect your Micro to the FPGA via general purpose I/O to support upgrade and general comms.    --- Quote Start ---  need a way for occasional updates (without having to disassemble the machine, pluggin in additional hardware, running special software, ...)  --- Quote End ---   I assume you'll have some sort of interface to the micro - UART/network. So, there'll be no need to dismantle anything.  If you really must use MAX10, look through Altera's recommended method of field upgrade. App Note 741 - "remote system upgrade for max 10 fpga devices over uart with the nios ii processor (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an741.pdf)". You don't necessarily need a Nios II processor and the interface need not be a UART (this simply demonstrates how few pins are needed. You can do much better with a micro sitting right next to the FPGA). However, the principle is there and this is the route Altera recommend.  Cheers, Alex

[Altera_Forum]

Thank you for your justified recommondations regarding the Cyclone (which we are using in other products), but in this case the decision towards MAX10 is already taken. 

   --- Quote Start ---   Solely for programming?    --- Quote End ---    Not solely for programming, we will use the User Flash Memory too.    --- Quote Start ---   If you really must use MAX10, look through Altera's recommended method of field upgrade. App Note 741  --- Quote End ---    Thank you for the App Note 741, I have not known this before. This solution has a few drawbacks, e.g. we intended to overcome the need for the initial programming using external JTAG hardware. That is another reason for using JTAG instead of any other (user-defined) communication channel (which exist, as you assumed, btw).  Altought the MAX 10 is "compliant to the IEEE-1532-2002" (handbook) there is no "IEEE 1532-Compliant BSDL File" available here: https://www.altera.com/support/support-resources/download/board-layout-test/bsdl/_1532/bsd-1532.html  I would expect the programming routine being described there, although not easily human readable, but it is missing anyway. Do you know why? Or where I can get it instead?

[Altera_Forum]

Hi 'markuss'. 

 Alex gave us an excellent explanation and I think he's righ. But, if you must use JTAG to program MAX 10 over a host microprocessor, there is the JAM STAPL solution too. I don't know if is the way for your aplication, but take a look: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an586.pdf.  https://www.altera.com/support/support-resources/download/programming/jam.html (Jam STAPL byte-Code Player)  regards.

[Altera_Forum]

OK - the decision to use MAX 10 is fine, it can be a fine solution. However, I maintain that supporting an upgrade path in the field, via JTAG, is shortsighted. The lack of documentation in this respect should be ringing alarm bells. 

   --- Quote Start ---  we intended to overcome the need for the initial programming using external JTAG hardware  --- Quote End ---    So you need to maintain this path for the purposes of manufacturing. Why over complicate it by also giving the micro access to the same JTAG nets? You will be mightily frustrated should your prototype come back and JTAG doesn't work because you've over complicated access to, and compromised, those nets.    --- Quote Start ---  That is another reason for using JTAG instead of any other (user-defined) communication channel (which exist, as you assumed, btw).  --- Quote End ---    So you do have another route into the MAX 10 FPGA(s). Upgrade the MAX 10 FLASH via this route and leave JTAG available for manufacturing and development.    --- Quote Start ---  I would expect the programming routine being described there, although not easily human readable, but it is missing anyway. Do you know why? Or where I can get it instead?  --- Quote End ---    See the max 10 fpgas bsdl files (https://www.altera.com/support/support-resources/download/board-layout-test/bsdl/max-10.html) page for the relevant BSDL file. However, you will NOT be able to reverse engineer the FPGA programming from this. This file describes the FPGA's I/O cells and the registers that can be accessed via JTAG. It will not tell you how to use them or how to program the FPGA.  If you really, really, REALLY must use JTAG then you should consider reverse engineering a Serial Vector File (SVF), which you can generate from Quartus - see here (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07222008_677.html). These files are what a manufacturer is likely to use to program up and FPGA, via JTAG, using their own JTAG equipment.  However, I still maintain the best route for upgrading MAX 10 FLASH, in the field, is via your micro<->FPGA interface, not JTAG.  Good luck with your development.  Cheers, Alex

[Altera_Forum]

Thank you, I will think about this again...

[Altera_Forum]

--- Quote Start ---  OK - the decision to use MAX 10 is fine, it can be a fine solution. However, I maintain that supporting an upgrade path in the field, via JTAG, is shortsighted. The lack of documentation in this respect should be ringing alarm bells.    So you need to maintain this path for the purposes of manufacturing. Why over complicate it by also giving the micro access to the same JTAG nets? You will be mightily frustrated should your prototype come back and JTAG doesn't work because you've over complicated access to, and compromised, those nets.    So you do have another route into the MAX 10 FPGA(s). Upgrade the MAX 10 FLASH via this route and leave JTAG available for manufacturing and development.    See the max 10 fpgas bsdl files (https://www.altera.com/support/support-resources/download/board-layout-test/bsdl/max-10.html) page for the relevant BSDL file. However, you will NOT be able to reverse engineer the FPGA programming from this. This file describes the FPGA's I/O cells and the registers that can be accessed via JTAG. It will not tell you how to use them or how to program the FPGA.  If you really, really, REALLY must use JTAG then you should consider reverse engineering a Serial Vector File (SVF), which you can generate from Quartus - see here (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07222008_677.html). These files are what a manufacturer is likely to use to program up and FPGA, via JTAG, using their own JTAG equipment.  However, I still maintain the best route for upgrading MAX 10 FLASH, in the field, is via your micro<->FPGA interface, not JTAG.  Good luck with your development.  Cheers, Alex  --- Quote End ---     Hi Alex,  I am trying to generate SVF file for MAX10 from Quartus but I found that those options under Device and Pin Options -> Programming Files has been shaded out.  Do you face this issue before?  Regards, Soo Cheng