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Altera_Forum
Honored Contributor I
1,671 Views

MAX10 mixed VCCIO for configuration pins

Hi 

 

I am using a dual-supply MAX10 with banks 1a, 1b and 2 powered from 2.5 V and all remaining banks, including bank 8, from 3.3 V. I cannot find anything in the documentation suggesting that this is wrong however running the IO assignment analysis process from within Quartus produces the following warning: 

 

Warning (169202): Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs. 

 

I assume it does not like the fact that my JTAG header (which is connected to IO bank 1b) is running at 2.5 V whilst the configuration control/status pins, eg, nCONFIG, nSTATUS, etc, (which are all in IO bank 8) are all running at 3.3 V. Can you confirm that this arrangement is completely acceptable? I realise it's a warning rather than an error but I don't really see why it is even a warning. 

 

Thanks in advance 

 

Tim
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2 Replies
Altera_Forum
Honored Contributor I
216 Views

Hi, 

 

Yes you are correct. 

Warning can be removed by  

Settings > Device > Device and Pin Options... > Configuration > Configuration device and un-checking the box "Force VCCIO to be compatible with configuration I/O voltage". 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
216 Views

Thank you for your reply, it's useful to know we do not have a problem with our hardware design.  

 

Not a big problem but for your information, unchecking the "Force VCCIO to be compatible with configuration I/O voltage" option in the device settings does not seem to suppress the warning when building the FPGA. For reference, we are using Quartus Prime Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition. 

 

Regards 

 

Tim
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