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Honored Contributor I

MAX10 no response after power cycle

We have been using altera parts for many years, and the VHDL design I am currently using has been in production for over 5 years with a MAXII. 

Compiled it for the 10M04SCE144 and all is well until we execute an extended power off cycle. A short power off cycle, (less than 20 seconds) the system comes up and running as normal. 

With an extended power off cycle, (more than 2 minutes), the FPGA no longer responds after power up. 


Using SignalTapII, I see the same behavior. After programming the FPGA,and running SignalTapII, all is well. 

Close SignalTapII, execute a short power off cycle, reopen SignalTapII, all is well. 

Follow the same process with a long power off cycle, When Reopening SignalTapII get "Invaid JTAG configuration" and "instance not found". 


To correct the error, also fixes issue with FPGA non response to IO, Connect with programmer and execute a Verification only, will verify correct, and corrects problems. until next power cycle. 


I have checked power supply ramp up and down, reset signal timing, found no problems. 


I have even disabled all configuration pins on the FPGA as I am not using them and left floating. 

In screen shots, 3.3V is top, Reset line is bottom. 

What could be the problem here? 


Found the issue, resolved
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3 Replies
Honored Contributor I

Can you share what the problem was? Could help somebody else down the road.

Honored Contributor I

New to the FPGA world, but been working with Altera PLD for many years. 

The issue was the configuration pins, even though you can disable the configuration pins in the project settings, the config pins must still have pull ups on the ConfigSel, nConfig, and nStatus lines or intermittent behavior is seen on power up. 

Future note, if dual purpose is used on these pin, not sure all cases would actually work properly.
Honored Contributor I

I believe the two pins that need pullups are nSTATUS and CONF_DONE. 


nCONFIG can be tied to the power rail rather than needing a pullup resistor. (per the 'Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines' document). 


I believe CONFIG_SEL is ignored if you are only using single configuration images (I have it tied to GND on my design, but the documentation suggests it's not used unless the flash contents calls for it).