MLVDS backplane interconnection

[Altera_Forum]

Hi all. 

I'm developing an industrial FPGA interconnect back plane. I need to communicate over a single differential lane, with a master that initiates a request and one out of several slaves that responds.   Serial data rate should be greater than 150 Mbps (16 bit parallel data, at least 8/10 words per microsecond bursted on bus). I want to use MLVDS transceivers, because they meet the target speed and are the best pick for noisy environment. Unfortunately I can't transmit a clock, so over the single differential lane should be present data + embedded clock.  Master is based on Altera Cyclone IV (connected to a ARM A8 cpu); slaves have one Altera FPGA (low cost, maybe MAX10 family):  http://www.alteraforum.com/forum/attachment.php?attachmentid=11153&stc=1   Question is: I don't know nothing about hot to serialize/de-serialize the parallel data inside FPGA (yellow box in the image above): - Altera IP cores use embedded transceivers (as far as I understood searching around Megawizard plugin manager) - Altera LVDS communication is available only in "full featured" devices; cheap MAX10 family doesn't support serdes IP cores. - I can't find half duplex ser/des IP core.  Do you have any suggestion as kick-start (demoboards, reference designs, etc...)?  PS: I've already read AN522 , but it discusses the I/O configuration using BLVDS pins (not present in MAX10 family).