Hi,
Is there a way to have two avalon buses on a single FPGA. I understand that there is avalon interconnection fabic and there can be multiple masters on the bus with multiple slave units with slave side arbitration. Needed your comments on this.. Thanks Sheshi連結已複製
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Thanks!
How can we do this? Assuming that i have multiple Avalon masters and multiple slaves, i understand that, all these masters & slaves are connected on a common avalon bus. If iam going with a point-to-point communication b'n masters & slaves, can the configuration mentioned below is possible? Avalon bus 1 -- datawidth(32) Address_bus1 - Master 1 -- Slave1 Avalon bus 2 -- datawidth(128) Address_bus2- Master 2 -- Slave2 Avalon bus 3 -- datawidth(16) Address_bus3- Master 3 -- Slave3 There is no mention of multiple avalon busses in the avalon specification document. hopefully there can be multiple data buses on the same avalon switch fabric, but not the bus as whole {i mean address, data and control planes}. Correct me if i am wrong. -sheshiI know for a fact that you can have independent sections in a single SOPC with different datawidth's. In our system, we have a NIOS processor with a dedicated data/instruction ram, then we also have a couple of other masters that only access a 128 bit wide ram.
The two systems are not directly connected to each other, and have overlapping address space, so I'm pretty sure the address and control buses are independent. But I haven't looked inside to verify. PeteTo answer the question how: By default, when you add a new slave it the SOPC system tends to hook it up to the primary master (NIOS) data bus.
We added all masters and slaves in the system, then disconnected and isolated the masters and databuses by clicking on the interconnect diagrams and manually hooking them up the way we wanted. (IE only having the masters talk to the slaves we wanted them to talk to.) Once the connections were complete, we could then change the different sections address ranges where we wanted them to be. Pete