Max II Config Complete Detection

Altera_Forum · ‎02-03-2010

I currently have an issue where I am trying to separate a power-on reset from a "software reset". Basically, in our system we have a DSP that accesses several registers in a MAX II CPLD via SPI. The DSP is also responsible for powering up the CPLD. When the DSP asserts the supply enable to the CPLD, it also asserts a RESET line to the CPLD. When a power-up occurs, and the reset is asserted, I want the CPLD to set all registers to their default values. This is considered a "power on reset". However, the DSP can also assert the RESET line at any time during normal operation, which is a "software reset". This Reset should cause the CPLD to clear only certain registers, while others retain their value. Only when the RESET is accompanied by a device configuration should everything be set to defaults.

Now, the MAXII datasheet claims that all registers are set to 0's when configuration completes and the device is released to user mode. So what I do, is create two signals - config_complete and config_complete_d. At my first positive clock edge after configuration, I set config_complete to a 1. At the next edge, config complete_d follows.

In my code that is responsible for resetting the registers, I say:

if(config_complete && ~config_complete_d) "reset registers to all 1's".

For some reason though, this code is not executing, and the registers are starting with all 0's, instead of the intended all 1's. I think it may be getting optimized away. I know it is a bit of a weird scenario, and the real solution would be to have a power_on_reset chip asserting a GPIO to do this. However, it is too late in the game for that, and I need to try to figure out a way to discriminate between this power-on reset, and the "software reset".

Anyone done something similar, or have an idea how to create a "config_complete" detector for the MaxII?

Any help is greatly appreciated.

Altera_Forum · ‎02-03-2010

First thought would be to make sure config_complete and config_complete_d have a default value of '0'. If the default is not defined it may default it to '1' and never enter your reset state.

Altera_Forum · ‎02-03-2010

To reset all registers to a defined state, you don't need a reset controller however. Simply assigne initial states to the signals. They are converted to power on set/resets. You should consider however two points:

MAXII (as well as many newer FPGA families) has only asynchronous reset, not set.

- This means, the compiler inverts the register polarity internally to achieve an asynchronous set.

- You can't use both, asynchronous set and reset for a register

In some cases, you may want to assure the reset to be synchronously released. Then you need a kind of reset controller. Without an external reset input, I mostly use a reset counter, that should even resist an uncleanly starting clock. In VHDL, it looks like below:

signal start	: INTEGER range 0 to 7 := 0;
...
IF rising_edge(clk) THEN
  IF start < 7  THEN
    start <= start + 1;	
    reset <= '1';
  ELSE
    Reset <= '0';
  END IF;