Max10 3.3V Differential Input

[RS_CEI]

Product: 10M25DCF484C7G
Environment: Quartus Prime Version 21.1.0 Build 842 SJ Standard Edition

Max10 3.3V LVDS input. We have a clock on our custom board that is coming in with ~700mV of swing at a Vcm of 2.26V. We were unaware at the time of design that there are no 3.3V Differential options on the Max10.  It is unfortunately not enough swing for the LVTTL/LVCMOS minimum low/high of VIL=0.8V(max) / VIH= 1.7V(min) even if we had the Vcm perfectly centered between.

Is there an ini file or some way to trick quartus into using this clock? Maybe LVDS for one input to a 3.3V bank and we can ensure we are AC coupled and adjust termination for swing/Vcm?

[FvM]

Hi,
if you want to operate within specified I/O standards, a resistive divider or AC coupling with bias resistors can bring input voltage into LVDS25 range. It's also possible, although beyond datasheet specifications, to assign LVDS25 to an I/O bank with 3.3V actual supply voltage. According to my observations, input common mode range increases respectively.

[RS_CEI]

Hi FvM,

I have other I/O on the bank that does need to be at 3.3V so I can't switch the whole bank over to 2.5V in hardware. So you are saying to change Quartus bank voltage to 2.5V and assign LVDS25? The datasheet specifications on the recommended bank voltage has a maximum of 2.625V (for VCCIO 2.5V) how do you know this will not damage or shorten the life of the part? I would assume the LVTTL/LVCMOS would stay at 3.3V with an actual bank voltage of 3.3V, but are there parts that could get damaged if it is expecting 2.5V I/O?

Thanks for the reply!

[AqidAyman_Intel]

Hello,

As far as I know, there is no .ini that can be used to enable LVDS with 3.3v VCCIO. To use that clock, I would suggest adding external circuitry to lower the common mode voltage plus the swing. I would not recommend using those voltage levels directly to LVDS buffers, because I think this is an out-of-spec situation and even if it works, we can't be sure that it will work all the time and for how long it will work. Also, I believe that if the VCCIO of the bank is set to 3.3v and you assign LVDS to one of the pins, Quartus will not compile successfully. Another option is to change the VCM from the third-party chip. Some chips are able to change that value using some registers.

Thanks.

[RS_CEI]

Hi AqidAyman! Thanks for the reply.

Design definitely doesn't compile with LVDS (or any differential assignment) on 3.3V VCCIO bank. So you are saying there are two options here:

1. Adding external circuitry to lower common mode voltage plus swing.
2. Changing the VCM of the IC sending the clock.

I can DC Block and change the VCM/Swing before the Max10 using external circuitry, but I'm not sure how either of these will allow us to use the differential clock in a 3.3V VCCIO bank.