Max7000 register power-up level

[Altera_Forum]

I am using Quartus II with a MAX7000s EPM7128. This is related to previous question I asked at http://www.alteraforum.com/forum/showthread.php?t=23753 

 I am using the Assignment Editor to assign a Power-up Level of Low to several 8-bit registers (implemented with DFFs). I have also disabled the "Power-up Don't Care" option under assignments>settings>Analysis & Synthesis Settings.  This does nothing to control the power-up state of the registers. The registers seem to power-up with random bits set. For troubleshooting I also tried setting the power-up state to High, and no change.  Interestingly, I tried this on 6 different identical boards (in house design) and each board behaves differently, two of them power up with all registers set to 0 every time, and the others are random with most bits going to 0 and a few getting set to 1.  Any ideas? Am I missing something? Is there something overriding the power-up level assignment? I checked and double checked and there is nothing that should be inadvertently loading the registers.  Thanks, James 

[Altera_Forum]

Is the description from your original post (regarding OR gate operation) still true? If so, there's either a hidden problem in your logic definition or the logic is implemented incorrectly by Quartus. In any case, I don't think that anyone can fix it from a distance without having the exact design and being able to check in in the real hardware. 

 The varying behaviour with different boards seems to suggest a problem of input signal timing or supply voltage ramp.  The datasheet clarifies, that MAX7000 registers allways power up low, so power-up high just means inverting the register output but doesn't change anything to the power-up logic itself.

[Altera_Forum]

Yes the original description is still true. I've attached an image of a schematic of the logic to make it a little more clear. The circuit in question is a VME bus interface module. 

 The two clear signals are /reset and /init which go into an Or gate. /reset is generated by an external VME bus master which is supposed to be low for at least 200ms per the VMEbus specifications, although I have not verified this. /init is generated by the control status register (csr) at the bottom. Interestingly the csr, always initializes correctly.    The CLK signals for each register, RCKL1, RCKL2, RCKL3 and RCKL4 are formed by combinational logic from the VMEbus address, and they are mutually exclusive. /Bwrite is from combinational logic from the VMEbus control signals.   On Power-up latch80n instances 94,99,103,109 all have random bits set. latch8on instance 109 always powers up to 0. If I remove /reset or /init, every register powers up to 0 most of the time (probably 9 out of ten), otherwise the registers power up wrong around half the time. If I set the power-up level attribute to each latch in the assignment editor to low it helps somewhat.    http://i1046.photobucket.com/albums/b466/jgflynn/latch_pic.gif   EDIT: uploaded corrected photo

[Altera_Forum]

I found the problem. I set NOT Gate Push-Back to off and the problem went away. 

  edit: Not fixed see post below

[Altera_Forum]

Once again it seems the problem is fixed only on some of the boards. We have 22 boards total and I have only tested this on six of them, but so far the following holds true…. There are two slightly different CPLD part number batches, the CPLDs with one number power up correctly when I disable 'not gate pushback' and 'power-up don't care', the others still initialize randomly.  

The CPLDs that work are labeled:  EPM7128SQC100-10  W BEJ240807A  VEJ 24766810  303WABEOK    The CPLDs that don't work are labeled:  EPM7128SQC100-10  BEJ240249a  VEJ2453314  303WA2ZOC    The CPLD part number is EPM7128SQC100-10, does anyone have any idea what the numbers below the part number are and why it would cause the CPLD to behave differently on powerup? Again this has only been tested on six boards so I'm not totally certain that the numbers have anything to do with it.