Maximum avaliable frequency with the altera_gpio at Arria 10

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Hello! 

I try to create very simple DDR register with help of AlteraGPIO megafunction. This project must generate clock (200 MHz) and periodical data pulse at rising edge of clock, which has 90 degree phase relationship with data (see attachment wave.png). Thats code of my project:  module test_sdc ( input bit ref_clk, output bit clk_out, output bit data_out ); // Generate reset signal for PLL bit reset_cntr = '0; bit reset_pll; always_ff @(posedge ref_clk) begin if (reset_cntr != '1) reset_cntr <= reset_cntr + 1'b1; end assign reset_pll = reset_cntr != '1; // Generate clock and reset bit reset_n, core_clk, out_clk; pll pll_25_200 ( .locked ( reset_n ), .outclk_0 ( core_clk ), .outclk_1 ( out_clk ), .refclk ( ref_clk ), .rst ( reset_pll ) ); // Generate data signal bit data_cntr; always_ff @(posedge core_clk) begin if (!reset_n) data_cntr <= '0; else data_cntr <= data_cntr + 1'b1; end assign data_flag = data_cntr == '1; // Create DDR output for data and clock ddr_reg ddr_data ( .ck (core_clk), .din ({1'b0, data_flag}), .pad_out (data_out) ); ddr_reg clk_data ( .ck (out_clk), .din (2'b01), .pad_out (clk_out) ); endmodule  Also I defined constraint for TQ:  create_clock -period 25MHz derive_pll_clocks derive_clock_uncertainty create_generated_clock -name ext_clk_pin -source ] set_output_delay -clock -max 0.5 set_output_delay -clock -min -0.5 set_output_delay -clock -max 0.5 -clock_fall -add_delay set_output_delay -clock -min -0.5 -clock_fall -add_delay set_false_path -setup -fall_from pll_25_200|iopll_0|outclk0 -rise_to ext_clk_pin set_false_path -setup -rise_from pll_25_200|iopll_0|outclk0 -fall_to ext_clk_pin set_false_path -hold -fall_from pll_25_200|iopll_0|outclk0 -fall_to ext_clk_pin set_false_path -hold -rise_from pll_25_200|iopll_0|outclk0 -rise_to ext_clk_pin set_false_path -from -to   But compilation at Quartus Prime 15.1 was unsuccessful: design has a negative slacks for slow models (see TQ.png for detalies). For test purposes I compile that project for Cyclone 3 device (with change AlteraGPIO to ALTDDIO_OUT) - and it was compilated sucessful! Please, help me to understand why Cyclone 3 are more quickly that Arria 10