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Meeting hold time in Cyclone V Configuration with Micron Flash

kgupt8
Beginner
‎08-14-2019 05:54 AM
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I am using Cyclone V GX FPGA. Using ASx1 Interface to configure the FPGA through 128Mb Micron Flash. We just realized that Cyclone V in errata specifies min HOLD Time of 2.9ns on its AS_DATA1 pin. Since both Flash and dedicated Config pin are using falling edge of clock, so there may be issue in meeting hold time. 4 pins from FPGA are directly connected to Micron Flash , so there is no delay to take care of Hold time. Also Micron's clk_to_out delay for Data_out is 1.5ns. I wanted help to know Whether I can adjust the delay on dedicated config pins inorder to meet hold timing. Please help.

 

Regards

Kaps

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JohnT_Intel
Employee
‎08-15-2019 03:15 AM
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Hi,

 

Unfortunately there is no way to make the changes in delay on the pin as this is a dedicated pin. You will need to modify your board in order to meet the specification

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