Hi there, I want to generate a 2 port RAM using MegaWizard.I need that the rdaddress and rdenable inputs without register them first, because this will cause a one clock cycle delay and the internal bus that I use expects that the result shows on the next rising edge of clock when rdaddress and rdenable is high. I also found that write port has to be registered no matter whether M20K or MLAB is used. Read port is different. If I use M20k, I can not choose "no registered" read port. If use MLAB I can. I wonder is that means I can not use M20K in my situation? Thanks for any comments!
--- Quote Start --- No, all rams need a registered read address. --- Quote End --- Thanks for your comments. I actually found one user manual from Altera. One page 4-12, it shows that the read data shows at the very first rising edge of clock cycle. However, if it is registered, it should happen at the second rising edge of clock cycle, since the first rising edge is to fill the input register. https://www.altera.com/content/dam/a.../ug/ug_ram.pdf Is the manual incorrect here?