Memory Access via JTAG (MemTest)

[Altera_Forum]

The JTAG IF via USB Blaster offers the possability to gain access to FLASH, Nios and other stuff. 

 Does anybody know how to gain access via JTAG to any address location, read and write ? The task is to write a memory test like walking 1's and 0's that runs via JTAG if the FPGA is already running (nios halted)  nios wiki has some tcl scripts but the doc there does not make it clear to me if some of them supports such an access and what must be inluded in sopc.  or does anybody now a link to some pdf explaining how to do this ?  thanks in advance.

[Altera_Forum]

Hi Michael, 

 Here are some possible solutions: 1) Add (eventually interupt activated) debugging software to your nios applications to communicate with the JTAGuart. 2) Write some kind of debug application on the nios and communicate with the JTAGuart. 3) For some on-chip MegaFunctions you can use the TCL scripting facility of the "In-System Memory Content Editor". See page 16.8 (http://www.altera.com/literature/hb/qts/qts_qii53012.pdf) in Volume 3 of the Quartus-II handbook.

[Altera_Forum]

thank, just had tried this from nios wiki : 

 Starting System Console •From SOPC Builder, click Tools --> Launch System Console  •From Nios II 8.0 Command Shell, type "system-console"  &#9702;If you have the Quartus Project handy, try "system-console -jdi=<quartus_proj>.jdi". This will give System Console more information about the JTAG nodes in your system. Reading and Writing Memory with a Nios II Processor This assumes that only one Nios II Processor exists in the system. If one or more Nios II's or a JTAG Avalon Master exists, then in Step 1 you might have to change the list index to get the correct master.  0. <From System Console shell> 1. set nios [ lindex [ get_service_paths master ] 0 ] - might need to change the index number if there are > 1 masters. 2. open_service master $nios 3. processor_stop $nios - the Nios must be in debug mode to access memory  4. master_read_memory $nios 0x00000 4 - Read 4 bytes starting at address 0x00000. 5. master_write_memory $nios 0x00000 [ list 0xaa 0xbb 0xcc 0xdd ] - Writes 0xaa to address 0x0, 0xbb to addr 0x1, etc. 6. close_service master $nios - release SLD Node lock when finished.  so with this i could read and write without the need to modify the target design, just plug in the jtag ...

[Altera_Forum]

You don't even need a Nios/NiosII! There is a "JTAG to Avalon MM bridge" component that implements an Avalon MM Master for talking to all of your Avalon slaves. Please go through this training (http://www.altera.com/education/training/courses/oemb1117), if you're really interested in using System Console. It has a nice example attached to it that doesn't use NiosII and most (all?) of the typical usage modes. 

 Cheers,  - Ura

[Altera_Forum]

hi, 

i'm having a strange problem, i used following commands   1) nios2-configure-sof -c USB-Blaster -d 2 mysof.sof  <device programmer show success>  2) nios2-download -c USB-Blaster -d 2 -r -g myelf.elf  <elf downloaded and verified>  3) system-console  <console opens>  <now inside system console> 4) set mydev [lindex [get_service_paths device] 0] /connections/USB-Blaster [USB-0]/EP2SGX90  5) device_load_jdi $mydev myjdi.jdi  6) lindex [get_service_paths processor ] 0  /connections/USB-Blaster [USB-0]/EP2SGX90/cpu  7) lindex [get_service_paths master ] 0  /connections/USB-Blaster [USB-0]/EP2SGX90/cpu  8) set myproc [lindex [get_service_paths processor ] 0]  9) open_service processor $myproc  Jul 8, 2009 4:33:13 PM com.altera.systemconsole.scripting.ScriptEngine$27 execute SEVERE: Target must be configured before use  Target must be configured before use  ======================================================= my system just have one NIOS-II and no other jtag master. I have configure the device and downloaded the ELF...so what configuartion is left?  Note:I'm using - PCI Express Development Kit, Stratix II GX Edition - Quartus/NIOS-II 9

[Altera_Forum]

Is there more than one item in your JTAG chain?

[Altera_Forum]

There is a MAX-II CPLD as well.

[Altera_Forum]

I thought so. I was able to duplicate your error on two different boards (each with multiple items in the JTAG chain) I submitted this to factory and they are investigating. Not that it is a great solution but... If you are able to "bypass" the CPLD in the JTAG chain with jumpers the problem will go away. I will post any patch or "workaround" I receive.

[Altera_Forum]

in what order are your devices on the jtag line ? 

in earlier designs i did, the fpga was after a maxII that lead to some problems and we hat to be aware of the fpga position in the jtag line. if your fpga is not the first device on the jtag line, check wheter you can assign its device position number to your script. i am unshure if the 0 is the device number, beginning to count from 0 nowadays all new designs have the fpga as the first device in the jtag flow

[Altera_Forum]

Altera has kindly provided a JAR patch for this issue. It will be permanently fixed in V9.1. 

 The default location for the file is here C:\Altera\90\nios2eds\sdk2\lib, just replace the existing one.   Best Regards,

[Altera_Forum]

where did you get this fix from ? 

i haven't found it on altera ftp nor altera web site. and quartus V9.x is no option as long there is an issue with EPCS that was not fixed in SP1. latest quartus without this bug is quartus 8.1. if quartus sp2 fixes this bug is unknown to me.

[Altera_Forum]

Are you saying you can't see the file I attached to the post? I got it directly from the engineer who created it. I don't know if he is going to post it in the solutions database or not. I know the patch works with 9.0 SP2. It may work with 8.1. I have not tried it.

[Altera_Forum]

no, the file you posted is okay, but the KB has no entry about that. 

If this patch is for 9.0SP2 i doubt i will work for 8.1 and i guess there will never be a patch for 8.1 as the only solution mentioned is to upgrade

[Altera_Forum]

--- Quote Start ---  in what order are your devices on the jtag line ? in earlier designs i did, the fpga was after a maxII that lead to some problems and we hat to be aware of the fpga position in the jtag line. if your fpga is not the first device on the jtag line, check wheter you can assign its device position number to your script. i am unshure if the 0 is the device number, beginning to count from 0 nowadays all new designs have the fpga as the first device in the jtag flow  --- Quote End ---    First thanks for reply (you too sniper). The Stratix-II GX order was 2nd, as you can see in the command:  1) nios2-configure-sof -c USB-Blaster -d 2 mysof.sof  <device programmer show success>  2) nios2-download -c USB-Blaster -d 2 -r -g myelf.elf  <elf downloaded and verified>  But inside system console, the FPGA is recognized as device 0:  4) set mydev [lindex [get_service_paths device] 0] /connections/USB-Blaster [USB-0]/EP2SGX90  I will check the patch and see if it works for me

[Altera_Forum]

One option that does work is adding an avalon jtag master in addition to nios. It allows system console to read and write memory, external or internal through this master. 

 By the way, the patch does not work with Nios 9.0 sp2.  Regards