Memory Interface Grouping Assignment

[Altera_Forum]

Hello, 

 I got error as below    Error: I/O "DQBH[5]" has a memory interface specific sub-block, but has no memory interface grouping assignment specified  Info: stratixiii_io_config atom "dq_dqs_xyz:inst30|bidir_dq_1_io_config_inst"   The PinPlaner automaticly group this signal with other three signals from (x4).   Are there away or option to set "memory interface grouping assignment"?   Thanks

[Altera_Forum]

I have a very similar error during placing & routing in the high performance ddr2 sdram controller. Did you figure out why that happens by any chance?

[Altera_Forum]

Same problem here. If you find out, let me know.:mad:

[Altera_Forum]

to VietPath 

OUTPUT_ENABLE_GROUP will be helpful to group the pins.  Run the tcl pin assignment script before compilation with necessary modification will be helpful to get rid off the problem during fitter operation. Best Regards, Cheevu

[Altera_Forum]

Hello, 

 I got pretty the same problem (and I am quite a newbi in Quartus/Verilog).  I generated my NIOS with SOPC Builder.  (I was not able to post the image of the schematic)  I ran the TCL scripts given by SOPC : -altmemddr_0_phy_ddr_pins.tcl -altmemddr_0_pin_assignments.tcl  I made clk_n bidirectionnal  I noticed the in my .qsf file this kind of lines    --- Quote Start ---  set_instance_assignment -name OUTPUT_ENABLE_GROUP 2113154281 -to mem_dq_to_and_from_the_altmemddr_0[0]  --- Quote End ---  But I still have this kind of error:     --- Quote Start ---  Error: I/Os have a memory interface specific sub-block, but have no memory interface grouping assignment specified  -> Error: I/O "datas[63]" has a memory interface specific sub-block, but has no memory interface grouping assignment specified   --- Quote End ---  Where datas the bidir port I put on my schematic.  Can someone post his assignment file please.  Cordially  trax

[Altera_Forum]

i am having a similar error with ddr3 uniphy.  

we have been using xilinx ddr2 in our products. i am exploring an opportunity using ddr3. how do you specify grouping for dq and dqs? can an fae help resolve this? thank you.............................................  Error: I/Os have a memory interface specific sub-block, but have no memory interface grouping assignment specified  Error: I/O "mem_dq0[0]" has a memory interface specific sub-block, but has no memory interface grouping assignment specified File: ~altera/mcu/rtl/mcu_altdqdqs.sv Line: 1368  Info: stratixiv_io_config atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|pad_gen[0].config_1"  Info: stratixiv_output_phase_alignment atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].data_alignment"  Info: stratixiv_output_phase_alignment atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].oe_alignment"  Info: stratixiv_output_phase_alignment atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].oct_alignment"  Info: Half-rate stratixiv_ddio_out atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].hr_to_fr_oct"  Info: Half-rate stratixiv_ddio_out atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].hr_to_fr_oe"  Info: Half-rate stratixiv_ddio_out atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].hr_to_fr_hi"  Info: Half-rate stratixiv_ddio_out atom "mcu:mcu0|mcu_controller_phy:controller_phy_inst|mcu_memphy_top:memphy_top_inst|mcu_memphy:umemphy|mcu_new_io_pads:uio_pads|mcu_altdqdqs:dq_ddio[0].ubidir_dq_dqs|output_path_gen[0].hr_to_fr_lo"

[Altera_Forum]

OK. 

in ALTMEMPHY Design Tutorials emi_tut_ddr.pdf: 1) On the Tools menu, click Tcl scripts. 2) Under Libraries, select <variation_name>_pin_assignments.tcl 3) Click Run.  made the error go away. wish the error message showed how to fix it.

[Altera_Forum]

The thing is the synthesizer is stupid, don't try to use Verilog as top level instantiantion, use schematic. 

  --- Quote Start ---  Hello,  I got pretty the same problem (and I am quite a newbi in Quartus/Verilog).  I generated my NIOS with SOPC Builder.  (I was not able to post the image of the schematic)  I ran the TCL scripts given by SOPC : -altmemddr_0_phy_ddr_pins.tcl -altmemddr_0_pin_assignments.tcl  I made clk_n bidirectionnal  I noticed the in my .qsf file this kind of lines  But I still have this kind of error:   Where datas the bidir port I put on my schematic.  Can someone post his assignment file please.  Cordially  trax  --- Quote End ---