Memory mapping of PTM , CTI-0, CTI-1 for ARM A9 in altera SOC

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Memory mapping of PTM , CTI-0, CTI-1 for ARM A9 in altera SOC

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Hi,

I have been checking the documentation on cyclone V and ARM website for base address of MPU debug component i.e CTI-0 , CTI-1 , PTM-0 and PTM-1. I am not able to find it on any documents. Let me know if I have missed any documents . Let me know the memory mapped configuration registers for the MPU debug component.

Thanks

Pratik

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