Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Metastablity

Altera_Forum
Honored Contributor II
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I came across on the solution(reduce the failure rate) for the metastablity by using double synchronizer. 

 

Somehow i don understand the statement below: 

Place FFs close together to allow maximum time for META to reslove 

 

Can someone explain? i would appreciate if the explanation include the timing diagram. 

 

thanks
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Altera_Forum
Honored Contributor II
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Placing the FFs close together shortens the path time between them. The clock period is of course fixed so the time between clocks is the META time plus the signal propagation time cannot be longer than the clock period or the input to the second FF will not be stable. 

 

So path time = META time + propagation time and the shorter propagation time allow more time for META to resolve. 

 

clk.............|--|...........|--|.... 

input..........|------------------- 

META.........|---------|......... 

prop.......................|--| 

FF2.............................|-----
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