Migrating devices - Power and Ground on I/Os?

[Altera_Forum]

When using device migration, I find that I/O pins on some devices are supposed to be power or ground on other devices. Is it okay to connect I/O pins to power or ground on my board?

[Altera_Forum]

There are no spreadsheets available, you'd have to make those yourself. Altera doesn't do it because there are too many combinations between all of the devices. The best way, and sure way to get it right, is to use Quartus II. Just make a simple project with minimal I/O pins, choose a device and add all of the migration devices you want. Compile the project and you'll have a <project_name>.pin file with all the user available pins shown as GND* or GND+. The power and ground pins will be defined as well. There's your migration compatible pin list.

[Altera_Forum]

Yes you can connect I/Os to power and gnd, set them as inputs in your design. I have done device migration by doing this in the past with no problems. There is usually one part which has more IO and one with less, make the schematic for the one with less IO then a double check to make sure is what I have done.

[Altera_Forum]

Yes you can connect I/Os to power and gnd. In addition to device migration this is a somewhat common practice for creating programmable ground or VCC pins to help minimize SSN by assigning as output driving GND connected to GND and output driving VCC connected to VCC on the board. It won't damage your I/O pins when they are defined as inputs in your design.

[Altera_Forum]

By the way , I have a question about "Unused Pins Driving Ground / VCC" 

 When we design DDRII interface using IO Standard of SSTL18 Class I In order to reduce SSN , I have tried to put all the unused pins to be user-assigned Outputs driving Ground (In experimental result , Ground Bounce seems more significant then VCC sag) And then on the PCB , these unused pins are connected to Ground  However , Fitter gives a error message that It violates the VREF rules (I guess Quartus treats the pins as output although they are driving ground directly)  And then finally , I choose not to place Pins in design file for these unused pins In Assignment --> Device --> Device and Pin Options --> Unused Pins --> As output driving Gorund  Comparing these two approach , do they give the same result ? I mean , do they help in reducing SSN in same extent ?  Thanks

[Altera_Forum]

You can bypass the fitter error by using the "Output Toggle Rate" assignment, give it a value of "0 MHz" for any of your user assigned VCC or GND I/O pins. This tells the fitter that the output never toggles, thus it won't violate the Vref rule. 

 Whether you assign the pin as a programmable ground, or let Quartus II do it by assigning all unused pins as outputs driving ground, you will have the same result as far as reducing SSN. The nice thing about user programmed pins is you can assign some to VCC to help with VCC sag. But you're right, ground bounce is typically worse than VCC sag.

[Altera_Forum]

Hi Desert Rat , 

 Thanks very much for your answer !!! The VREF rules and programmable VCC/GND really annoys me ...

[Altera_Forum]

--- Quote Start ---  When using device migration, I find that I/O pins on some devices are supposed to be power or ground on other devices. Is it okay to connect I/O pins to power or ground on my board?  --- Quote End ---     It's better to use Quartus II device migration setting. It will take care of the power and ground pins for you. If you are using the IO pin and it is supposed to be power pins on another device migration package, you'll get the warning or error message while running the fitter.