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Mismatch of requirements from JEDEC with recommendations Intel(Altera)

AndrewBI
Beginner
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I am studying the workings of DDR memory, in particular the recommendations for PCB layout. One of the intel documents (Table 1–24; Page 70) has the following wording: "Propagation delay of clock signal must not be shorter than propagation delay of DSQ signal at every device"

However, if this is compared with the requirements from JEDEC(Registration required for reading,Table 69, page 175): 

JEDEC.png

 Where tCK is Average Clock Period = 8ns.

In the JEDEC standard I can clearly see the  negative time tdqss relative to the rising edge tCK, which says that the DQS line is shorter. Is Intel(Altera) not DDR compliant or am I missing something?

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