Missing virtual jtag documentation

[Altera_Forum]

Hello, 

 I started to use the sld_virtual_jtag Megafunction for low level debugging puposes, using Tcl interface with quartus_stp. Now I'm considering possible operation with non-Altera JTAG interfaces. The virtual jtag user guide says:    --- Quote Start ---  If you are building a debugging solution for a system where a microprocessor controls the JTAG chain, the SignalTap II embedded logic analyzer cannot be used because the JTAG control has to be with the microprocessor. By learning the low level controls for the JTAG port from the Tcl commands, you can program microprocessors to communicate with the sld_virtual_jtag megafunction inside the device core.  --- Quote End ---    Does this mean, instead of documenting the coding of virtual jtag ir and dr shift instructions, Altera suggests to "hack" the information from Tcl operation by applying the -show_equivalent_device_ir_dr_shift option? Sounds somewhat silly to my opinion.  The point is, I can easily learn the commands to assemble the virtual ir and dr shift instructions for a fixed virtual jtag configuration from this method. But the configuration may change and other virtual jtag node types (stp, source&probe, in-system-memory) can be added and modify the virtual jtag node configuration. I would prefer to have a tool, that is able to identify virtual jtag instances from read-back node configuration as quartus_stp obviously does.  This would imply understanding the jtag hub programming to some extent, which Altera apparently didn't wanted to disclose up to now. I don't see, that this information, effectively present at users fingertips, should be classified confidential.  Best regards and Merry Christmas  Frank

[Altera_Forum]

Hi, 

 Thanks for your quick reply. I don't think my problem is caused by a specific scenario of internals I am trying to access but rather the Virtual Jtag Instance is not being detected somehow.   Every time I try to use the "device_virtual_ir_shift" and "device_virtual_dr_shift" command in Tcl, it gives me an error. But I tried the exact same thing on altera's DE0 board and everything works fine there. So I don't know if there is any additional thing I need to do to make it work. I am still using an Altera Download Cable to access my own PCB.  Anyone have any suggestions or any ideas? Anything would help at this point lol  Thanks. Jack

[Altera_Forum]

Did you check, if standard virtual JTAG components (e.g. Signal Tap II, Source & Probe, In-system memory content editor) are working with your board? If not correctly, you have a hardware issue with your JTAG interface.

[Altera_Forum]

--- Quote Start ---  Did you check, if standard virtual JTAG components (e.g. Signal Tap II, Source & Probe, In-system memory content editor) are working with your board? If not correctly, you have a hardware issue with your JTAG interface.  --- Quote End ---    You were right! I tired using Signal Tap II and it didn't work with my board but it worked on the Altera's Development board.   I guess the problem is a hardware issue with my JTAG interface but I tired using the JTAG Chain Debugger in Quartus II Programer, it was able to detect the FPGA (I'm using Stratix II EP2S15F484C5) on my board correctly.  Do you have any suggestions as to how I would go about debugging this hardware issue with the JTAG interface?  Much Appreciated, Jack

[Altera_Forum]

The problem is usually related to TCK signal quality. Some JTAG actions, e.g. configuration download are working, other actions are not working. 

 In one case, JTAG was working well, after I put a small capacitor (22 pF) in parallel to the TCK pull-down resistor (near the FPGA).

[Altera_Forum]

--- Quote Start ---  The problem is usually related to TCK signal quality. Some JTAG actions, e.g. configuration download are working, other actions are not working.  In one case, JTAG was working well, after I put a small capacitor (22 pF) in parallel to the TCK pull-down resistor (near the FPGA).  --- Quote End ---    Thanks for your reply. Do you think there might be a problem with the SLD Hub? Because when I tried to get the SLD_NODE information by issuing the HUB_INFO Instruction like you have described in your earlier post, all I get returned is 0x0F. So I guess that means that no sld node is being detected somehow. So I am thinking there might be a problem with the SLD_HUB.  So is there a way for me to check if the SLD Hub is even implemented? and if it is, is it implemented correctly?   Thank You, Jack

[Altera_Forum]

--- Quote Start ---  Because when I tried to get the SLD_NODE information by issuing the HUB_INFO Instruction like you have described in your earlier post  --- Quote End ---    I don't know if it is directly related to your problem, but things changes in this regard since we started this thread. Altera already disclosed and published the relevant information about SLD.  There are even a couple of design examples provided by Altera.    --- Quote Start ---  So is there a way for me to check if the SLD Hub is even implemented? and if it is, is it implemented correctly?  --- Quote End ---    There is a debug pane at the Quartus compilation report. The pane is enabled when you use the Virtual Jtag megafunction.

[Altera_Forum]

The reported issue of Signal Tap not working with a specific board hardware is very likely a pure hardware problem. There have been previously problems with Virtual JTAG functions, that haven't been correctly operated by Quartus tools under certain conditions (not related to SignalTap), but those are gone since a Version 8 service pack, if I remember right. I hope that no new JTAG bugs have been introduced with Quartus 10, which I'm not using yet. 

 P.S.: The last VJTAG related Quartus bug, I'm aware of, has been fixed with Quartus V9.0. It involved failure of SFL in certain combinations with other VJTAG instances. The bug had been located in the programmer tool operation, not the VJTAG logic itself.

[Altera_Forum]

Thanks for your help, I got it to work! 

 However, I am running into a different problem. Like I mentioned earlier, I am using the VJI to program a flash device, so I am shifting values into my BSR (Boundary Scan Registers) that are connected to the SCK,SI,CS and SO pins of my flash device. So basically, I am continuously shifting a value of 0 and 1 into the BSR cell that is connected to the SCK. Also, shifting my data to the BSR cell to the SI pin and etc.  Now, I created a script which basically contains the device_ir and device_dr shift commands. When I run this script and try to measure the frequency of the BSR register that is connected to SCK, I am getting like 250 Hz. I tried to measure the TCK coming out of the VJI as well and that is running at around 1 MHz.  Do you guys know why there is such a significant decrease in the frequency of my SCK. I only have 3 boundary scan cell (one for SCK, one for SI, and one for CS). Is this decrease in speed due to the device_dr shift command? I have attached the RTL map for my design.  Please Help, Thanks

[Altera_Forum]

I guess, the script execution speed is the limiting factor in this case. Virtual JTAG operation is already slow due to the involved overhead, but it achieves an acceptable throughput when driven by the Altera tools, e.g. SFL/PFL prgramming or SignalTap II.

[Altera_Forum]

I figured out a why to make it faster! 

 The device_ir and device_dr shift command will try to capture the current data in the registers before shifting the new data in. By invoking the -no_captured_ir_value and -no_captured_dr_value, I am able to get it to run at 100-200 KHz. What a difference!  Thanks again for all your help!