Mixing FPP and AS for programming FPGA

[Altera_Forum]

Hi, 

I'm having trouble using the Quartus II software, so I'm going to leave it for the moment.  The system I'll be designing is with the Stratix IV FPGA, using our own user logic as well as our own CPLD and a supported CFI flash memory. We also want to have the remote system upgrade facility as well.  I've been reading through the datasheets and I understand the FPP (Fast Passive Parallel) and AS(Active Serial) modes. However I need to be able  to program the FPGA using FPP, AS is simply too slow. It's ok for remote system upgrade. So I'm wondering what's the best way to go about switching between these two modes without manually changing a DIP switch on the board.  Also I'm unclear about the transactions for the remote system upgrade. I understand that the system goes into a reset a serial configuration device loads the upgrade onto the FPGA via the user logic. What i'm unclear about is the connections used for this and if this programs the  upgrade file to the CFI Flash memory as well. Would Altera's MAX II work as the serial configuration device? I really don't want to use yet another IC on the board.   Thanks in advance. -Mike P.

[Altera_Forum]

It's unusual (except for Dev Kits that allow to experience different techniques) to have more than one configuration scheme implemented in a design. In most cases, it doesn't make any sense, to my opinion. 

 FPP or flash storage with MAX II configuration controller are preferable for larger configuration files, e. g. more cost effective. I'm not sure, if device programming is considerably faster. Configuration itself is faster, but also isn''t an issue with AS for most applications. But your requirements may be specific.  Regarding remote upgrade, the rich choice of options and operatig modes is possibly confusing at first sight, but the technique is documented verbosely in device handbooks and application notes.  Remote upgrade normally implies a user defined communication channel, e. g. ethernet or any other connection already existing in your design as a parallel or serial databus. If none exists, you probably don't need remote system upgrade and could use a local JTAG interface as well.

[Altera_Forum]

I will second what FvM is saying.  

 Go ahead and choose FPP as your configuration scheme. Then write your CPLD code so that it can pull and load different images from the flash to configure the FPGA. Then just make sure you leave a couple of pins between the FPGA and CPLD so the FPGA can inform the CPLD what image it wants loaded and trigger a reconfig. Your CPLD code can handle the logic of defaulting back to a safe image if the FPGA fails to configure.  We actually do this same thing now on one of our designs (except we use passive serial).  Jake

[Altera_Forum]

Hi there guys, 

Thanks for the advice. I will be going ahead with FPP mode anyway. I think I got a little confused while going through the documentation and app notes with regards the remote system upgrades. For the Stratix IV, it says it only supports AS. However as FvM has said, that I can go ahead and use Ethernet as a parallel databus.  Unfortunately, I couldn't find any mention for connecting to an ethernet connection in the documentation. I assume this will be a parallel connection as well. Is it also possible to accept this upgrade through another microcontroller as well? If so, do you know through which pins it will communicate as I need to make sure our microcontroller can support it. Also, do you know the steps through which an ethernet upload occurs. Initiation, download, upload and rebooting?  Thanks again for your help

[Altera_Forum]

Some clarification is in order. 

 Beginning with Stratix II, Altera began to offer a reconfiguration controller inside the FPGA. This is a hard piece of silicon which will actually control part of the reconfiguration process. This is the component you read about with regards to Stratix IV. However, many many people perform remote configuration without the use of this controller.  Here is what you need:  1 - A configuration method which supports dynamic selection of an FPGA image. In your case, you are talking about a CPLD which interfaces to flash memory, selects an image from flash memory and programs the FPGA. 2 - A method for allowing the FPGA to dynamically add/change the stored FPGA images. The easiest way to do this is to make sure the FPGA is also connected to the Flash device. 3 - Connections between the CPLD / FPGA that allows the FPGA to instruct the CPLD a) what image it wants loaded, b) when to start reconfiguration. 4 - Some method of determining whether the desired reconfiguration was successful or not. This can be done either in the CPLD or FPGA or some combination of the two.  So with these things in mind, I have left one thing out. That is the method that you use to actually transfer new FPGA images to the board and store them in the flash. FvM has suggested ethernet. It could also be USB, serial, PCI Express, whatever. You are responsible for handling that part. There is no "core" that will transfer FPGA images from ethernet to your flash device. Does not exist. The point I'm trying to make is that at this point you must design the system. You've reached the separation point between mechanism and implementation. The documentation is no longer of use.  If you use ethernet, you will then need to implement a TCP/IP stack. The simplest way of doing this is to use a NIOS processor and select a TCP/IP stack of your choice. Altera provides the InterNiche TCP/IP stack. Then you will have to decide how to actually transfer the files (FTP, TFTP, your own protocol, ...).  Jake