Mixing VHDL and Verilog

[Altera_Forum]

I have the Terasic Cyclone V board. They generate a Verilog top module with the board signal names that connect to the pins. 

I have a VHDL file that instantiates this Verilog top module to get access to the board signals. However, when I program the board my VHDL doesn't work.   I created a VHDL file with the board signal names and got rid of the Verilog file. That works.  How come my VHDL code did not work when Verilog was the top file with the board signal names?

[Altera_Forum]

--- Quote Start ---   I have a VHDL file that instantiates this Verilog top module to get access to the board signals   --- Quote End ---   That does not make sense (at least to me). Why would you instantiate the Verilog top-module in your VHDL, as then its no longer the top-level module?!!  The key requirements for your top-level design are that its port names match the pin constraints. Had you created a top-level VHDL file with *exactly* the same port names as the Terasic example *AND* used the same pin assignments, then your top-level VHDL is identical to Terasic's. If you do not like their port names, then you can change them in your top-level VHDL *AND* in the pin assignments.  You can use the Pin Planner to view the pin assignments. You can export the project as a Tcl file to see those constraints.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  That does not make sense (at least to me). Why would you instantiate the Verilog top-module in your VHDL, as then its no longer the top-level module?!!  The key requirements for your top-level design are that its port names match the pin constraints. Had you created a top-level VHDL file with *exactly* the same port names as the Terasic example *AND* used the same pin assignments, then your top-level VHDL is identical to Terasic's. If you do not like their port names, then you can change them in your top-level VHDL *AND* in the pin assignments.  You can use the Pin Planner to view the pin assignments. You can export the project as a Tcl file to see those constraints.  Cheers, Dave  --- Quote End ---   All of my code is in VHDL. The only thing that isn't is the Verilog module that has the board signal names. I did what you said and made a VHDL file with the board signal names and got rid of the Verilog. The goal is not to have to do that extra task.   I would like to keep the Verilog module as Terasic generates it and just use my VHDL file to instantiate it to get access to the signals. As i pointed out, that doesn't work. The Verilog file is the Top-Level Entity. I even tried making the VHDL file the Top-Level Entity. Neither works.  Why not. The signals from the VHDL connect to the Verilog signals so it seems reasonable to me that the electrical connections are there.

[Altera_Forum]

--- Quote Start ---   Why not. The signals from the VHDL connect to the Verilog signals so it seems reasonable to me that the electrical connections are there.  --- Quote End ---   If the signal names are identical, then yes, it would work fine, however, its a bit redundant right?  I also code in VHDL. My personal philosophy with reference designs (Altera and Terasic) is that they are a starting-point. I take their golden-top reference design, synthesize that project (which does not always succeed), and then export all the project constraints. I take the pin assignments for the board and move that to a separate script (constraints.tcl), and then create a top-level 'basic' design, and use that as a template for all other designs.  Take a look at the bemicro_cv_examples.zip file in this thread:  http://www.alteraforum.com/forum/showthread.php?t=43992  What I'd recommend you do, is create a top-level pin constraints script based on the Terasic reference documentation, and your own VHDL top-level design, and they you no longer need to use any of the Terasic resources.  If this sounds too complicated, point me to the Terasic board you have, and I'll give you more detailed instructions.  Cheers, Dave  PS. If the file is not too big, you can zip it (or Quartus archive it) and send it to me, and I'll see if I can see what is wrong. My forum name is my email address.

[Altera_Forum]

--- Quote Start ---  If the signal names are identical, then yes, it would work fine, however, its a bit redundant right?  I also code in VHDL. My personal philosophy with reference designs (Altera and Terasic) is that they are a starting-point. I take their golden-top reference design, synthesize that project (which does not always succeed), and then export all the project constraints. I take the pin assignments for the board and move that to a separate script (constraints.tcl), and then create a top-level 'basic' design, and use that as a template for all other designs.  Take a look at the bemicro_cv_examples.zip file in this thread:  http://www.alteraforum.com/forum/showthread.php?t=43992  What I'd recommend you do, is create a top-level pin constraints script based on the Terasic reference documentation, and your own VHDL top-level design, and they you no longer need to use any of the Terasic resources.  If this sounds too complicated, point me to the Terasic board you have, and I'll give you more detailed instructions.  Cheers, Dave  PS. If the file is not too big, you can zip it (or Quartus archive it) and send it to me, and I'll see if I can see what is wrong. My forum name is my email address.  --- Quote End ---    Thanks. I try your suggestion.  The board is the Cyclone V GX Starter Kit.

[Altera_Forum]

--- Quote Start ---   The board is the Cyclone V GX Starter Kit.  --- Quote End ---    This Terasic board:  http://www.altera.com/products/devkits/altera/kit-terasic-cyclone-v-gx-starter.html  This looks similar to their DE-series of boards. Terasic usually have a golden-top reference design. I usually synthesize that, export the design as Tcl, and then write scripts like that for the BeMicro-CV design I linked to above. I then go through the schematic and check the pin assignments and add any missing pin constraints. You should be able to duplicate something similar for your own use.  Cheers, Dave