Modelsim compiling error:(vcom-11) Could not find work.stratixiv_hssi_components

[Altera_Forum]

hey,everyone! 

I am doing simulation with modelsim.When compiling the libraries before runing the do file, i am confused of the error below:# ** Error: (vcom-11) Could not find work.stratixiv_hssi_components.# ** Error: ./altera/stratixiv_hssi_atoms.vhd(112): (vcom-1195) Cannot find expanded name "work.stratixiv_hssi_components".# ** Error: ./altera/stratixiv_hssi_atoms.vhd(112): Unknown expanded name.# ** Error: ./altera/stratixiv_hssi_atoms.vhd(114): VHDL Compiler exiting# ** Error: D:/EDA_Tools/modeltech_6.5e/win32/vcom failed. But in fact i have do the tcl script of compiling stratixiv_hssi_components.vhd.Could anybody knows why?Thank you very much! Here is my tcl script: if ![file isdirectory verilog_libs] {    file mkdir vhdl_libs    set vhdl_dir "./altera"    vlib vhdl_libs/altera_V     vmap altera ./vhdl_libs/altera_V   vcom -93 -work altera $vhdl_dir/altera_primitives_components.vhd   vcom -93 -work altera $vhdl_dir/altera_primitives.vhd     vlib vhdl_libs/lpm_V     vmap lpm ./vhdl_libs/lpm_V   vcom -93 -work lpm $vhdl_dir/220pack.vhd   vcom -93 -work lpm $vhdl_dir/220model.vhd      vlib vhdl_libs/sgate_V     vmap sgate ./vhdl_libs/sgate_V    vcom -93 -work sgate $vhdl_dir/sgate_pack.vhd   vcom -93 -work sgate $vhdl_dir/sgate.vhd     vlib vhdl_libs/altera_mf_V     vmap altera_mf ./vhdl_libs/altera_mf_V      vcom -93 -work altera_mf $vhdl_dir/altera_mf_components.vhd   vcom -93 -work altera_mf $vhdl_dir/altera_mf.vhd     vlib vhdl_libs/stratixiv_V    vmap stratixiv ./vhdl_libs/stratixiv_V    vcom -93 -work stratixiv $vhdl_dir/stratixiv_atoms.vhd   vcom -93 -work stratixiv $vhdl_dir/stratixiv_hssi_atoms.vhd    vlib vhdl_libs/stratixiv_components_V    vmap stratixiv_components ./vhdl_libs/stratixiv_components_V    vcom -93 -work stratixiv_components $vhdl_dir/stratixiv_components.vhd  vcom -93 -work stratixiv_components $vhdl_dir/stratixiv_hssi_components.vhd

[Altera_Forum]

The error message indicates that the HDL code has a VHDL statement like 

 use work.stratixiv_hssi_components.all;  whereas you have compiled it into the VHDL library stratixiv.  Either compile it into the "work" library, or just edit the source to   library stratixiv; use stratixiv.stratixiv_hssi_components.all;  I've had to edit Altera's source before due to "work" being used in some files, and "stratixiv" being used in others.  Cheers, Dave

[chami]

I had the same error. I modified my .do file to compile the files into work:
vlib work
vmap work work
vcom -93 -quiet -work work \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/stratixiv_hssi_components.vhd \
$env(QUARTUS_ROOTDIR)/eda/sim_lib/stratixiv_hssi_atoms.vhd

and then I located the vhdl file where the error is occurring

and changed  

library stratixiv_hssi;
use stratixiv_hssi.stratixiv_hssi_components.all;

to

library work;
use work.stratixiv_hssi_components.all;

this is what I did!