Hi everyone!
I just got started with Altera, VHDL and all this stuff, so I'm not realy experienced. I have a system with NIOS II/e, jtag, some memory components and a custom peripheral. For debugging and simulation I use the NIOS II IDE for Eclipse, just the usual rightklick -> run as -> modelsim. Before I worked with NIOS and Avalon-Bus, I written some testbenches by my self, was actually nothing big, just some standard components I written during a VHDL tutorial.
Now with NIOS and Avalon-Bus I don't realy know how to write a testbench, there are all this arbitors, address alignment and so on. Thats why I used the IDE to simulate. I know I could use SignalTap-Analyzer, but there are already so many tools I have to get used to..... For a beginner it's realy hard to get started.
In my system, I was able to simulate everything so far but now I created a FIFO megafunction and added it as a component into my custom peripheral. So if I start modelsim simulation, all signals from the FIFO are undefined during the whole simulation. It's like ModelSim don't know the stucture of the component. I thought about writing testbench by my self but my peripheral uses avalon bus system, so I will have to add nios_system.vhd to the testbench, don't I?
Can anybody tell what I have to do so it's no more undefined? Do I have to add the FIFO.vhd somewhere?
Sorry if that's a stupid question and thanks.
Vlad
