Modelsim stuck in clock_div loop

[nome]

Hello

I am using Arria FPGA configuration from Max II CPLD with m29ew parallel flash x8 mode I am not using PFL megacore IP.

 I am using configure fpga by using  config_controller.vhd  from intel official 

please find in attachments

whenever I simulate these codes in Altera modelsim it will stuck in clock_div loop but when i press restart button in modelsim it will working good  

 kindly help us 

Thanks

Nome

[ShengN_Intel]

Hi Nome,

Based on the code provided, I had commented out those two modules config_state_machine and config_control_signal instantiations since not provided.

I noticed you have commented out all the RESET_n port connection and instantiated signal RESET_n to '0' with signal RESET_n : std_logic := '0'; So signal RESET_n will be always '0'. Also, signal MAX_EN is always '0' as well. That's why it will stuck in clock_div loop and keep resetting like below pic.

If instantiated signal RESET_n to '1' with signal RESET_n : std_logic := '1'; It will no more stuck in clock_div loop like below pic.

Thanks,

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[ShengN_Intel]

Hi,

Let me know if you have any further update or concern?

Thanks,

Best regards,

Sheng