Modelsim test vector to verify DDC/DUC working?

[Altera_Forum]

Hi there, 

 I'm looking for Modelsim version in verilog test vector to verify my DDC/DUC working good or not. By using signal generator as input and look at signalTap to see the result. But now, I really want to run entire in modelsim, so how can I generate test vectors as input in verilog, so I want to see in modelsim.   Thanks, Sean

[Altera_Forum]

first create some stimulus (using MATLAB, Octave, etc) and save it to a .txt file. then read the text file in your test bench and feed it into your system 

 you can see an example by creating a filter with FIR Compiler and taking a look at the generated test bench

[Altera_Forum]

Thank pancake, 

 Is there samples already done in Matlab to .txt file? I already have a framework in modelsim and needs to read inputs from .txt file. Yeah, this is what I'm looking for.