Multi IO voltage JTAG

[Altera_Forum]

My circuit is composed 4 Stratix4s per chain. 

 And each FPGA has multiple IO voltage. (see attachment picture) Vccio of each FPGA's bank1A is connected to 2.5V. So we connected pull-up to 2.5V.  But in my circuit there are no buffer or voltage translator.  i wonder my circuit conceptually is good for jtag operation without level translator.  Regards, JS Lee

[Altera_Forum]

Your JTAG chain is apparently all-2.5V. Why should it need a level translator? 

 Extensive JTAG chains might have problems with crosstalk of fast on-board to JTAG signals, particularly TCK. In this case, buffers can be helpful sometimes.

[Altera_Forum]

Hi FvM, 

 Thank you for your reply. It's lucky.  Anyway did you mean, even if other IO bank is connected different VCCIO, it is nothing to JTAG interface right ? Boundary cells are supplied from each VCCIO, so different IO bank might cause the error when signal shift to next cell. That's my concern.  I want to clarify my concept.  Thank you ~

[Altera_Forum]

This issue is solved. The circuit has no problme. The problem was "Damaged FPGA". Thanks a lot.