Multiple synchronous clocks and PLL in digital audio application

[Altera_Forum]

I am about to make a digital audio transceiver in a Cyclone V device and I am a little bit stuck on the clock strategy (and slightly rusty): 

 On the receiver the data is synchronized on a input bitclock, bclk (running at 64*fs) and a separate master clock, mclk (256*fs). They are normally synchronous to each others, but I have no control over that. The transmitter requires a clock of 128*fs. The question is how to design the clock-setup for this. I (can) use the Altera PLL from mclk to generate 128*fs (and 64*fs) clocks from the master clock.  What would be a good approach to the clock setup in this case?  1) Is it necessary with clock domain synchronizes when crossing two synchronous clock domains generated from the same PLL, but running at different speeds?  2) Are there any advantages from running a design using a single higher rate clock, than using multiple synchronous slower clocks? Granted, power consumption is affected.    3) On the receiver I see three clocking options:   a) Run the receiver on the input bitclock (64*fs), which later requires data clock synchronization on the collected data inwards the FPGA,  b) Run the receiver on mclk (256*fs) and use the incoming bitclock edges to advance the data reception.  c) Synchronize the incoming data against the PLL generated 64*fs clock. This requires that the assumption that the bitclock and the PLL generated clock is completely synchronous (which I doubt can be true).  Any thoughts around this would be appreciated  Thanks.

[Altera_Forum]

How much is 256*fs? 

 64*fs, 128*fs, 256*fs are simple doubling. if you run all on 256*fs then all you need is half/quarter enable and you get a clean single clock system.  You can apply multicycles if fmax gets in the way.  alternatively use all three clocks for better power (possibly not worth it) using PLL then all three clocks will be related.

[Altera_Forum]

256*fs is approx 24.5 MHz. fs is 96kHz.

[Altera_Forum]

--- Quote Start ---  256*fs is approx 24.5 MHz. fs is 96kHz.  --- Quote End ---    That is no problem, very slow in comparative sense and you should achieve fmax in cyclone V readily. So I will go for one clock system. generate enable at 1/2 and 1/4 rate and apply clcok to every process together with its enable. Do not gate the clock to divide it.

[Altera_Forum]

--- Quote Start ---  That is no problem, very slow in comparative sense and you should achieve fmax in cyclone V readily. So I will go for one clock system. generate enable at 1/2 and 1/4 rate and apply clcok to every process together with its enable. Do not gate the clock to divide it.  --- Quote End ---    Thank you.  Something like this does not gate the clock, right: (Again my HDL is rusty from years of pause)   -- Generate 1/4 rate enable DIV : process (clk) begin if clk'event and clk='1' then enable <= 0 when enable=3 else enable+1; end if; end process; FSM : process (...) begin if clk'event and clk='1' then if enable=0 then -- Progress the FSM next_state <= ... ... else -- Keep the current state next_state <= state; end if; end if; end process;

[Altera_Forum]

Given that there are plenty of PLL output counters, you could just use the same PLL to generate 3 clocks, each at the required frequency (256,128 and 64 * fs). Because they all come from the same PLL, the output counters are basically doing what a clock enable would do, producing synchronous clocks at the required frequencies.

[Altera_Forum]

--- Quote Start ---  Given that there are plenty of PLL output counters, you could just use the same PLL to generate 3 clocks, each at the required frequency (256,128 and 64 * fs). Because they all come from the same PLL, the output counters are basically doing what a clock enable would do, producing synchronous clocks at the required frequencies.  --- Quote End ---    Yes PLL is an option but in my opinion is an overkill remembring issues of lock, simulation, upgrading design, readability ...etc.  you can generate divide by 2 based on inverter:   process(clk) begin if rising_edge (clk) then en1in2 <= not en1in2; end process;

[Altera_Forum]

for en1in4 you need either use your counter(adder) in which case en1in2 is just bit0 of counter or invert as I did for en1in2 but convert to one pulse.

[Altera_Forum]

It looks my own VHDL is getting rusty. 

 I suggest this clean way for en1in2 & en1in4   process(clk) if rising_edge(clk) then en1in2 <= not en1in2; en1in4 <= '0'; if in1in2 = '1' then in1in4 <= not en1in4; end if; end if; end process;