NEEK version of Simple Socket Server Plus example

[Altera_Forum]

I have recently posted a NEEK version of this enhanced version of Simple Socket Server to the Nios Wiki, please follow the link below. 

 simple socket server plus (http://www.nioswiki.com/exampledesigns/simplesocketserverplus) - This example is an enhanced version of the Simple Socket Server (SSS) example that Altera has shipped for the past few years. The primary enhancements to this example are, enabled the InterNiche FTP server, enabled the InterNiche TFTP server, enabled the InterNiche FTP Client, enabled the InterNiche TFTP Client, enabled the InterNiche Telnet server, enabled the InterNiche console, enabled the InterNiche VFS file system, enabled the Altera ROZIPFS file system.

[Altera_Forum]

Hi rfrazer, 

 Is there a way to create our own username and password when using FTP without modifying the source code in the bsp folders?    I notice that the username and password is created using the add_user() function in ftpsport.c inside BSP folder. How do I call/use this function in user's application project?   Thanks for your help in advance.

[Altera_Forum]

Hi Rfrazer, 

 I didn't find your contact details and decided to wrote here about "Nios2UDPOffloadExample" posted on www_nioswiki.com/ExampleDesigns/Nios2UDPOffloadExample.  I’ve found this example and it looks great for my project. I have Stratix III development board www_altera_com/products/devkits/altera/kit-siii-host_html so I tried to modify it for my hardware. It was a partial success, it looks like Nios is working fine, but the packets are not transmitted in either direction.  In the log I have the following error – “TSEMAC SW reset bit never cleared!” in console messages:  ==================================================================== InterNiche Portable TCP/IP, v3.1   Copyright 1996-2008 by InterNiche Technologies. All rights reserved.  prep_tse_mac 0 Your Ethernet MAC address is 00:07:ed:ff:8f:10 Static IP Address is 10.0.0.1 prepped 1 interface, initializing... [tse_mac_init] INFO : TSE MAC 0 found at address 0x04000000 INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 1000, Duplex = Full TSEMAC SW reset bit never cleared! OK, x=10002, CMD_CONFIG=0x00002000  MAC post-initialization: CMD_CONFIG=0x00000248 [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created mctest init called IP address of et1 : 10.0.0.1 INET> Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) Created "PING client" task (Prio: 10) Created "FTP server" task (Prio: 6) Created "FTP client" task (Prio: 5) Created "telnet server" task (Prio: 7) Created "console" task (Prio: 9)  Stack is running...  Created "server handler 0" task (Prio: 18) Created "server handler 1" task (Prio: 17) Created "server handler 2" task (Prio: 16) Created "server handler 3" task (Prio: 15) Created "stream server" task (Prio: 19) Created "client handler 0" task (Prio: 23) Created "client handler 1" task (Prio: 22) Created "client handler 2" task (Prio: 21) Created "client handler 3" task (Prio: 20) Created "stream client" task (Prio: 24)  Built on Dec 20 2010 at 11:50:36  UDP Demo Menu installed and ready to use... Type "help" and "help udpoffload" for more information. ========================================================     So the software reset in Triple Speed Ethernet doesn’t work.  Can you or anyone advise me on where the problem can be?  At the moment I investigate the following options: 1. Timing problem. When the hardware is built, Stratix gives the following warnings on the timings:  ========================================================== Critical Warning: Timing requirements not met Info: Worst-case hold slack is -0.224  Info: Slack End Point TNS Clock   Info: ========= ============= =====================  Info: -0.224 -10.169 tx_clk_to_the_tse_mac_125M   Info: -0.167 -5.617 tx_clk_to_the_tse_mac_25M   Info: -0.167 -5.617 tx_clk_to_the_tse_mac_2p5M   Info: -0.058 -0.214 test_sys_sopc_inst|the_enet_pll|the_pll|altpll_component|auto_generated|pll1|clk[1] ==========================================================   Can it be that it leads to the problem with the software reset? On the other hand negotiation is partly successful, as evidenced by the log of connection with PHY.   2. Reset problem on the development board. It might be that there is a problem with reset on this specific board, as in another example that uses SGMI a bypass circuit for the hardware reset is inserted.  I’d be grateful for any help or hint. Best regards Argentum