NOOB DPRAM: Never get any data out

[Altera_Forum]

Hi All 

 Thanks in advance for any advice you can give me. FYI: I am not a student, I am a software engineer trying to experiment with an FPGA project.  problem description:    I cannot seem to get the Dual port ram mega function to perform (at all). I have reduced the problem to the smallest configuration possible. I have a VHDL state machine that attempts to write a single word to the ram. The state machine controls the clock, wren, address and data lines into the DPRam. In this sample it writes a single value to ram address 0 and stops doing anything. The written value never appears on the (unregistered) output. I am sure the issue is something simple in the configuration, but I have been unable to track down what could be wrong.  · The implementation is on a Cyclone III device. · Ram is 32 bits wide 64K words deep  The top level design uses a graphical block design to connect the state machine to the RAM and provide easy to read test points.  waveform See Attached document  top level diagram See attached document  the state machine code See attached document  dpram auto generated code See attached document