Need help to implement 2D array ROM in vhdl

[Altera_Forum]

Hi, 

 I wanna implement 16x16 array. each entry in that 2D array will be of 8 bit. so I wrote this.  TYPE SBOX is array (15 downto 0, 15 downto 0) of std_logic_vector(7 downto 0); // is this correct?  I also wanna access the particular entry in this 2D array. how should I define the address? say i wanna access the (10,5) entry which means 10th row and 5th coloumn entry.

[Altera_Forum]

Hi. 

 Was at this point some days before. Googled and found  http://stackoverflow.com/questions/17160878/how-to-declare-two-dimensional-arrays-and-their-elements-in-vhdl Helped me, so take a look.  Vlad

[Altera_Forum]

Hi, 

But my question is mainly regarding address. Since my array is 2D my address will be like (row,coloumn) type. Once i go to this address then i need to put this value as output. i'm not sure how to access the element of 2D array. Please help me if you have any idea regarding this issue. I tried to search but couldnt find yet. Thanks

[Altera_Forum]

You shouldn't create a 2d array like this if you want to infer altera ram. You need to make a 1d array and then concatenate the 4bit row and column addresses to make a single 8 bit address.

[Altera_Forum]

Isnt this 3D memory : 

 TYPE SBOX is array (15 downto 0, 15 downto 0) of std_logic_vector(7 downto 0); // is this correct?  You are defining a block of 16-bit x 16-bit and 08 of these blocks in 3rd dimension ???  So you will be giving it Row address ( range : 0-to-15) and Block address ( range : 0-to-7)

[Altera_Forum]

Hi, this was posted a while back, but I'll answer anyway: 

 Let's say you have a simple memory interface,with an Enable (toggle for R/W), Addr, and Data word, like this:  entity PageBuf_1 is  port (  Enable : in std_logic;  Address : in std_logic_vector (6 downto 0);  Data : inout std_logic_vector (31 downto 0)  ); end PageBuf_1;  Then your declared memory array would look like this, as declared within the Architecture:   architecture RAM of PageBuf_1 is   type MEMORY_ARRAY is array (0 to 127) of std_logic_vector (31 downto 0);  begin  ....  You declare you working variables from controlling access to memory, like this (which are local to the process); you're sensitive to any of the inputs changing value to execute the process:   process (Enable, Address, Data)   variable TEMP : std_logic_vector (6 downto 0);  variable VALID_ADDRESS : boolean;  variable Memory : MEMORY_ARRAY; -- you instantiate your declared array here.   Then, you'd have your process that controls reading the Enable line to determine whether the op is a read or write, from which you would index into the memory array to the specified location and either assign to, or read from, the location, like this:   if (Enable = '0') then  for i in 0 to 127 loop  if (SomeCompareFunctionIsTrue (TEMP, Address)) then  Data <= Memory (i);  VALID_ADDRESS := TRUE;  end if;  TEMP := FunctionToIncrementArrayIndex (TEMP);  end loop;  You'll have a similar If-Then block in the process for when you want to write to memory. Note that there are many styles of memory models, this is simply one example. Check out Ashenden's VHDL text where he discusses others. There are places where I've indicated that some "magic" need to be done with regards to incrementing and index and comparing two signals (which will likely involve VHDL type conversions).  Remember also that you need to consider boundary conditions and exceptions and what to do if you have an invalid address or enable value (since we're dealing with MVL9 here).  Hope this helps. have fun. regds, jim

[Altera_Forum]

How are you expecting this memory to work? It will not map to any hardware memories as it is asynchronous. I also do not undersstand the point of the for loop?  

 How does this post relate to the origional thread?