Need help with a constraint

[Altera_Forum]

I am working on a design which works, but I would like to finish the timing verification. 

 Specifically, I have an application that is talking to another board via an LVDS cable. To avoid complications, I chose to cut the data rate on the cable from 100MHz (the FPGA's native frequency) to 50MHz. Accordingly, my transmitter generates a clock to an external pin that is simply the PLL clock divided by 2. I still align all of the data using the PLL clock, however. (I don't use the generated clock internally)  Right now, I'm specifying all of the delays with respect to the PLL clock, not the generated clock, but I'm not sure that's correct. The data will be received at the far end using the generated clock. As such, I set about creating a generated clock based on the PLL clock, but I ran into some issues.  It does generate the clock, then warns me that there is no path between the two and that it is assuming the latency is zero. I then find a new, previously unlisted, clock, listed as a base clock, with no constraint on it.  I am using: create_generated_clock -name {Packet_Clock} -source [get_nets {U_PLL|altpll_component|auto_generated|wire_pll1_clk[1]}] -divide_by 2 [get_ports {Pkt_Clock}]  Pkt_Clock is the name of a pin, but I have specified other pin constraints using get_ports as well, so I'm not sure if that is related. Also, the code that generates the clock is in a sub entity. I noticed that the "found clock" is the output of that entity.  Lastly, before continuing, is this the right way to constrain these signals?  Thanks!