Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21616 Discussions

Need more detailed information for POR of MAX10

eng_jp
Novice
1,841 Views

I have read several Intel's document and , read similar question in community.

but, I could not get POR trip level from any documents.

This information is master peace for considering about Power off to Power on cycle.

Can I get it ?

0 Kudos
9 Replies
JonWay_C_Intel
Employee
1,829 Views

The trip point is not disclosed in any documentation. But if it were my design, I would use the Vmin in the Recommended Operating Conditions in the MAX10 datasheet.

Anything within the Recommended Operating Conditions are known to work well.
Anything below the Recommended Vmin would probably cause the device not to configure or non-functional.

0 Kudos
eng_jp
Novice
1,812 Views

Hi JonWay,

Thank you for your responce.
but, your last sentence have a some trouble in our development.
Last sentence use "would probably", it meen very unstable behavior during from zero volt to Vmin.
Does Intel guarantee that the POR circuit will work perfectly only when the supply voltage rises from zero volt?
Even if its true, but general products power restart not only rise from zero volt to recommended voltage.
Especially, when power off to on cycle is rapidly.

0 Kudos
JonWay_C_Intel
Employee
1,805 Views

The point im trying to make here is that as long as you are in the recommended voltage range, you are safe.

0 Kudos
eng_jp
Novice
1,799 Views

Ok, I understand what you mean.

Unfortunately, it is not my expect.

Well then could you present power off to on cycle sequence with the voltage level and time chart?

  

0 Kudos
JonWay_C_Intel
Employee
1,796 Views

Im not sure if this helps.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_pwr.pdf (Figure 3).

Perhaps, you can modify the Figure and sketch what you meant by "power off to on cycle"

0 Kudos
eng_jp
Novice
1,793 Views

Thank you. but as you described figure 3 is only power up cycle timing chart .

I need more information.
I attached simple timing chart of power off to on.(as single supply device)
could you answer about my question?

0 Kudos
JonWay_C_Intel
Employee
1,766 Views

I dont see the attachment. can you reattach?

0 Kudos
eng_jp
Novice
1,756 Views

hi,

I reattached the file.

 

0 Kudos
JonWay_C_Intel
Employee
1,739 Views

Replying to your questions in your diagram.

1) There is no device Vmin nor the duration of power off till next operation.

2) When you are operating below the recommended voltage, there is no guarantee for the device operation.

 

0 Kudos
Reply