New technique for pulse-width function on FPGAs

Altera_Forum · ‎02-26-2015

Hey all,

I am beginning to write a paper on a new technique for making pulse-width generators on FPGAs and I was hoping I could get some help connecting it to the current state-of-the-art and get suggestions for some applications.

My circuits use a new technique for laying out logic elements. Each circuit maps an input pulse of width w_{in} to an output pulse of width w_{out} through any arbitrary function f(w_{in})=w_{out}. The function f can be linear, quadratic, etc. and the resolution of the function is the minimum gate delay ~300ps. Again, this is an asynchronous circuit, so there is little to no latency.

What similar technologies are out there?

What applications can this have? I have been using it for an arbitrary pulse-width doubling circuit, but I suspect there are better applications in other areas of engineering.

I am also looking for helpful references for my paper.

Thanks!

Altera_Forum · ‎02-26-2015

The problem with anything asynchronous on an FPGA is that the delay is affected by many things: Process, voltage, temperature and Place and Route.

You can lock down the P&R yourself, but you have no control over the other three.

How will your circuit overcome these delay/timing issues?

Altera_Forum · ‎02-26-2015

I agree that temp., voltage, etc. can affect the timing of performing logic operations through the LUTs. Right now, my technique is just a proof-of-concept. I have developed the theory for why it should work and used the FPGA as a platform to test it. Ultimately, an ASIC could be created (with much more control over these parameters) for each pulse-width function that is desired.

Also, as far at the place and route, I can control these, in addition to the paths through the individual LUTs. However, these factors only lead to small discontinuities in the function f(w_{in}) = w_{out}, and the global function retains its shape even if I let the optimizer do its thing.

I guess I am asking, what could this be used for? What is similar that is out there?

Right now, the only types of pulse-width control circuits that I know of seem to be limited by the clock or some other on-board oscillator.

Thanks!

Altera_Forum · ‎02-26-2015

FPGA vendors do not recommend internal clock generation apart from those out of PLL/DLL.

FPGA delays are not reliable and change per PVT and routing changes per compilation. Though such delays can be used for coarse delay dependant applications.

Your idea should suit ASIC