Hey people ,
I'm new to fpga programming and been having a hard time fixing error 10170.
module button
(
input wire s3, s4, s5, s6,
output reg [6:0]seg ,
output wire select );
assign select = 1'b0;
if(~s3)
begin
seg=7'b0111111;
end
else begin
seg=7'b0000000;
end
if(~s4)
begin
seg=7'b0000110;
end
else begin
seg=7'b0000000;
end
if(~s5)
begin
seg=7'b1011011;
end
else begin
seg=7'b0000000;
end
if(~s6)
begin
seg=7'b1011111;
end
else begin
seg=7'b0000000;
end
endmodule
I keep on getting :
Error (10170): Verilog HDL syntax error at Adder.v(7) near text "if"; expecting "endmodule"
I'm using examples I found in books and on the web.
If I delete the 1st if statement , I get the same error again for the next if statement .
Any help will be very much appreciated.
