Newbie can't load data into fifo

[Altera_Forum]

I am new to FPGAs. I'm unable to clock data into the mega function FIFOs (both lpm_fifo_dc and dcfifo) in the simulator. I assume I'm doing something wrong, so I've retraced my steps for creating a simple schematic with only a dcfifo mega function and I/O pins. Here are the steps I've taken: 

 1. In a new Cyclone II project, create a new schematic file and add a dcfifo mega function with the following configuration: -dual clock -3 sync stages -add pins rdempty, rdusedw[], and aclr -set rdreq to act as a read request -disable overflow & underflow checking -generate netlist -create all file types  2. Create input and output pins to connect to all dcfifo I/O.  3. Under Assignments->Settings->Individual Clocks, create clock settings for rdclk and wrclk both for 100 ns periods.  4. Compile the design. The following 4 warnings occured but I doubt they're related to my problem: -Feature LogicLock is not available with your current license -No exact pin location assignment(s) for 24 pins of 24 total pins -Found 15 output pins without output pin load capacitance assignment -The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.  5. Generate the functional simulation netlist in the simulator tool.  6. Create the simulation waveforms for inputs: -All data pins were set high -wrclk was configured with a clock signal of 100ns period. -wrreq was forced high -rdreq and rdclk and aclr were all forced low  7. The simulator was run. The results show that rdempty is always high and rdusedw[] is always 0x00, even after 10 wrclk clock cycles. What step am I missing when creating this simulation?

[Altera_Forum]

You can't force rdclk low. Do you want the complicated explanation of how Dual-clock FIFO's work or do you want to take my word for it? 

 Jake

[Altera_Forum]

Sorry, I should have been more specific. You need an active clock on rdclk. 

 Jake

[Altera_Forum]

Hi Jake, 

I'm only trying to make the point that I cannot load data into the fifo. I intentionally do not clock rdclk, so I'm expecting that the fifo should fill up (rdusedw[] should not remain at 0x00).

[Altera_Forum]

rdusedw is registered and synchronous with rdclk, you need an active rdclk as Jake said.

[Altera_Forum]

--- Quote Start ---  rdusedw is registered and synchronous with rdclk  --- Quote End ---     Ok I didn't realize this. I changed the simulation to clock rdclk and now I see that rdusedw and rdempty display the correct values. Thanks a bunch.