Nichestack Tutorial Using Arria V GX starter board

[Altera_Forum]

Hi all, 

 Has anyone tried/succeeded in completing the nichestack tutorial provided on Altera's website using the Arria V GX starter board?  I have been working at it for a couple weeks now, and have been running into problems downloading the ELF file to the board. I have been receiving errors such as "Downloading ELF process failed" and "assertion "m_state==STATE_DEBUG" failed."  Also, more recently (after starting over from scratch and following the Cyclone V, I am getting run configuration errors that the system id and timestamp not found on target at expected base address)  Basically what I have been doing is trying to replicate the format of the cyclone V ethernet system also provided on altera's website (They have 2 different Cyclone III ethernet systems, as well as Cyclone V and Stratix IV ethernet systems provided). I have been using the cyclone V since it uses the same ethernet interface as the Arria V GX starter kit (10/100/1000Mb Ethernet MAC, with the RGMII setting). I have modified some of the components, such as clocks, memory and flash to accommodate settings such as address size and data size. I have also adjusted the pin planner to match the Arria V's pin layout. I have kept the verilog file the same, as it just connects the ports of the qsys system to the actual board pins. I have also used the cyclone III 3C120 C files provided in the nichestack tutorial files (since it uses RGMII). My program compiles in Quartus II 12.1 SP 1, and also builds fine in Nios II SBT, generating a .elf file. However, after run as -> nios II hardware, I find that the run configuration pops up and tells me the system ID hash and timestamp not found on target at expected base address.  I was wondering if there was anyone out there who was able to complete this tutorial using the Arria V, and if so if you could give me some insight on how you were able to complete it. Thank you all for your time.

[Altera_Forum]

Just check how your "reset" pin is connected to the system. Leaving it floating may cause something unexpected.

[Altera_Forum]

Alright, so I got past the issues I was having. I'm not sure what the exact problem was (I think timing issues with DDR3 RAM), but I made a couple of changes and it seemed to allow me to download to the board without any problem. However, a new issue has arose. After run as -> niosII hardware, it downloads to the board, and gets to the point where in the niosII console, it displays "[SSS_task] Nios II Simple Socket Server listening on port 30" (as expected). However, whenever I try to run the command "telnet 192.168.1.234 30" it stays in a state "Connecting to 192.168.1.234..." There is an LED blinking on my board as expected, but it seems like it is just not making the full connection. I am not using DHCP, rather I specified my own IP and gateway addresses in my simple_socket_server.h file and my local network settings explicitly (I have done this with the Cyclone III version and it worked just fine, so I know I did this part right). Any ideas on what may be the cause of this? It never says connect failed or anything, it simply always says connecting. 

 EDIT: I discovered an "Invalid MAC Address" message a few line above I did not see before. Checking this out, trying to find the MAC address of my device and hard code it into the C file  Thank you

[Altera_Forum]

If memory serves, there is a function "get_mac_addr()" in the file "network_utilities.c" that gets generated with the simple socket server demo app. The names might be off from what I just said, but you ought to be able to find it just mucking around. It's probably trying to pull it from a (non-existent) flash, and you can just hardcode it to whatever you like.

[Altera_Forum]

So I hardcoded the MAC address into iniche_init.c, and when I run as -> niosII hardware, it likes the mac address as well as the IP address I have assigned to niosII_simple_socket_server.h as well as manually through my windows network connections. It goes all the way down to listening on port 30 as expected still, but still not accepting the invitation from my telnet command. Could this be a problem in the c files? I have also tried pinging the IP address that is assigned to the board, but that fails as well. I really do not see any error messages, it just seems that for some reason the board does not want to communicate with my computer.

[Altera_Forum]

Well, you need to start with the basics, like: are any packets at all coming into your FPGA. It's kind of brute force, but the easiest way ( I find ) is to put SignalTap on the TSE Avalon-ST ports. You ought to get an SOP trigger for every Ethernet packet you directed at your board. 

There's other ways (software debugger) but I find this is the most direct way.  If you've got no activity on the TSE Avalon-ST ports, and everything is in the "ready" state, then you need to look further at the MAC address to make sure it's programmed correctly, and then beyond that start looking at the PHY's.  Alternatively, another way to debug it is to make sure that your board can actually transmit data that is seen by your PC (this will tell you the MAC address and the PHY are operating correctly); you can do this by modifying the hello world example to simply continuously send data on the network (e.g. while(1) sendto() ).

[Altera_Forum]

Hi ted, 

 First of all thank you for your reply. I appreciate your willingness to help me through my problem.  I have not tried SignalTap yet ( although I have heard a lot about it) so I think I will give that a try today. However, I have used Wireshark. I'm not sure if you are familiar with it, but its a good tool to use to check whether or not the computer can see the board or not (essentially another way of pinging it is how I see it). Basically what happens is there is a broadcast form 192.168.1.1 (IP I set manually to my computer) looking for 192.168.1.234 (IP I set manually to my Arria V GX board). There is no reply from the board, and what I have noticed is that in this program, the IP and MAC addresses of the computer are fine, but only the IP address of the board is correct. Wireshark shows the MAC address of the board to be all 0's. However, in NiosII SBT, when I run as-> niosII hardware, it displays the correct MAC address in the terminal along with the correct IP address.  So my question is the following: is there a setting in windows I need to go to, to edit the MAC address of the board? And could this potentially be the problem?  Like I said I will take look at SignalTap, and report back to this post with my findings.  Thank you

[Altera_Forum]

Yes, I am familiar with Wireshark. The fact that you see no activity from the FPGA side can mean one of two things: either the board is receiving packets fine but is having a problem transmitting, or the board is having trouble receiving packets so it doesn't know it's supposed to transmit anything. 

 Assuming transmit is working fine, then if you were using DHCP you would have seen at least a handful of packets come out of the board toward the PC every time you boot it. But with a static IP, you're waiting for the FPGA to receive a packet from the PC that it feels it needs to respond to (the query you are seeing in your Wireshark trace, for example).  At this point, you don't have enough information to say either way what is going on. This is where SignalTap might come in. It is at a much lower level of detail than Wireshark, but there is no wireshark equivalent within NIOS.  Regarding changing the MAC address of the FPGA in the PC side, no you don't have to do that (part of TCP/IP includes automatically figuring that information out). When you see that the PC has assigned 00's, that is simply placeholder meaning the PC hasn't gotten an answer yet.

[Altera_Forum]

--- Quote Start ---  Alright, so I got past the issues I was having. I'm not sure what the exact problem was (I think timing issues with DDR3 RAM), but I made a couple of changes and it seemed to allow me to download to the board without any problem. However, a new issue has arose. After run as -> niosII hardware, it downloads to the board, and gets to the point where in the niosII console, it displays "[SSS_task] Nios II Simple Socket Server listening on port 30" (as expected). However, whenever I try to run the command "telnet 192.168.1.234 30" it stays in a state "Connecting to 192.168.1.234..." There is an LED blinking on my board as expected, but it seems like it is just not making the full connection. I am not using DHCP, rather I specified my own IP and gateway addresses in my simple_socket_server.h file and my local network settings explicitly (I have done this with the Cyclone III version and it worked just fine, so I know I did this part right). Any ideas on what may be the cause of this? It never says connect failed or anything, it simply always says connecting.  EDIT: I discovered an "Invalid MAC Address" message a few line above I did not see before. Checking this out, trying to find the MAC address of my device and hard code it into the C file  Thank you  --- Quote End ---    I got the system running by using sram. system clock is 50MHz. however when I want to increase the frequency it fails. I modified based on stock remote update program.

[Altera_Forum]

--- Quote Start ---  I got the system running by using sram. system clock is 50MHz. however when I want to increase the frequency it fails. I modified based on stock remote update program.  --- Quote End ---    Hi sunxishan, thank you for your reply.  When you say you got the system running, do you mean the simple socket server using an Arria V GX starter board? And if so, what do you mean by the stock remote update program, and where did you make modifications (qsys files, quartus VHDL files, etc.)  My system actually uses 3 clocks: 100 MHz for the DDR3 memory, 125 Mhz for the ethernet system, and 50 Mhz for everything else (all based on what I read in the Arria V GX starter kit reference manual).  Thank you

[Altera_Forum]

And ted,  

 I am currently trying to use SignalTap with my design. I am looking for the Avalon ST ports you mentioned, and the ports I have monitored so far are (as defined in my system) enet_rx_d[3:0], enet_tx_d[3:0] (which are ports in the verilog file), and then also ports from the qsys files; the sgdma_tx and sgdma_rx (specifically out start_of_packet/end_of_packet and in start_of_packet/end_of_packet, respectively). Do these seem like the right signals? I figured since were trying to see if anything is recieved/sent by the board that these would be a good place to start.  I'm also trying to figure out how to set up the trigger for this application... I need to be careful as these are 25 min+ compiles. I ran it without setting up the trigger and the outputs were enet_rx_d[3:0] = 0100 and enet_tx_d[3:0] = 0000 constantly (but this is probably bad data)  P.S. If it would help to send parts of my design for reference (qsys files, verilog files) that is another possibility just let me know.  EDIT: After running signal tap with the help of a colleague, it appears to me that the FPGA is not recognizing any incoming signals from the ethernet cable, and therefore does not even know to send data back. Looking in more on where to start on this issue tomorrow morning.

[Altera_Forum]

Hi Everyone, 

 Just wondering if you got the Arria V GX starter board working with the ethernet communication.   I have been working on the basic web server and simple socket server on the Arria V GX starter board for a couple of weeks as well and haven't made it to the point of working yet. My version is Quartus 12.1sp1 with the older TSE MAC and I am using the DDR3 for the NIOS II core. It boots up and loads the initial Interniche stack but I have been having problems with the PHY initializing and also finding the external DHCP server.   The web server and simple socket servers work on the DE2-115 board without a problem so not sure what I am doing wrong.  Please let me know if you have any additional information on how to make this functional. My next step is to get the UDP packet offload project to work since my ultimate goal is a video streaming server with the RTP protocol.  Thanks, Kim :o