Nios ii cyclone 1 speed issues

[Altera_Forum]

Hi, 

 I am currently running into time issues with the nios ii cyclone 1 epc120 development fpga. I am using a control cycle of 100us in which I am now starting to a fair few calculations. These calculations are largely if statements with some shifts and single cycle multiplies.    The clock frequency on this board is 50MHz. I need to get about 25% more instructions executed in the same time period.   Does anyone know if it is feasible to increase the clock frequency to say 65MHz?   Failing that does anyone know how much more performance I would get out of using a cyclone 2 or 3 fpga. And would this require a whole new development board or just a new chip that will plug in?   Any help is greatly appreciated.   Thanks.

[Altera_Forum]

Hi crunchy225, 

   --- Quote Start ---  The clock frequency on this board is 50MHz. I need to get about 25% more instructions executed in the same time period.   Does anyone know if it is feasible to increase the clock frequency to say 65MHz?   --- Quote End ---     Although your board only has a 50MHz clock, you can generate other clock frequencies with a PLL block in your Cyclone, and this with some constraints on ratios for the frequencies with respect to the input clock.   Use the "MegaWizard" to add a "ALTPLL" module with the desired higher frequency. (e.g. 100MHz should probably still be OK).   Check the speed estimation of your design in the Quartus reports. Eventually use the TimeQuest timing analyzer to analyze the critical timing paths.   Hope this helps...