No logic elements although I have an output

[Altera_Forum]

Hello 

Please guide me why I don't see any logic element for the current code :  LIBRARY ieee; USE ieee.std_logic_1164.all; Use ieee.numeric_std.all; USE work.my_data_types.all; -- to define array of input ( package )  ENTITY test IS PORT ( clk: in std_logic;  OutResult: out signed(9 downto 0)); end test;  Architecture behave of test is  Signal Im : Array2D:=(("0010000111","0001111110","0001001101","0000000000","0000000000"),  ("0001001111","0010000100","0000101100","0000011011","0000000000"),  ("0001011101","0010000100","0000100111","0000101001","0000000000"),  ("0001011101","0010000100","0000100111","0000101001","0000000000"),  ("0000000000","0000000000","0000000000","0000000000","0000000000"));   signal Bufftemp:Array2D; signal Buffsig:signed(9 DOWNTO 0); begin   Process (clk)  variable i,j:integer range 0 to 7:=0;  begin if (clk' event and clk='1') then for j in 0 to 1 loop for i in 0 to 1 loop   Bufftemp(2*j,2*i+1)<= Im(2*j,2*i+1) - 5;   end loop; end loop; end if; Buffsig<=Bufftemp(i,j); end process;   OutResult<=Buffsig;   end behave;

[Altera_Forum]

--- Quote Start ---  Initially, you may do better using the mega wizard to generate the ram, then you know for sure that a ram will be used. Infered ram has to match the correct behavioural template to be correctly inferred, otherwise logic will be inferred. Review this document for coding styles: https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf  --- Quote End ---    I didn't call memory using mega wizard before , so I will read the document carefully and try it. I am really thankful to you. You are really helping me.

[Altera_Forum]

--- Quote Start ---  Initially, you may do better using the mega wizard to generate the ram, then you know for sure that a ram will be used. Infered ram has to match the correct behavioural template to be correctly inferred, otherwise logic will be inferred. Review this document for coding styles: https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf  --- Quote End ---    Dear Admin, I have created a memory ( but without wizard) and read it as follows PROCESS (clock) variable i:integer range -1 to 31:=-1;  BEGIN IF rising_edge(clock) THEN i:=i+1;  q1 <= ram1(i); -- output ( ram is mif file of 32 element, each of 3 bits)  END IF; END PROCESS;  ram1 is external file that I successfully read its data , each element read in one clock cycle. However , I am trying to get the first three elements after they read to apply a mathematical equation to them in next clock cycle. when I tried to create registers to carry the values , I unintentionally read three element at the same time so the memory transferred to logic elements.  My question is , How can I store only three elements and add them and then I get another three to add while keep reading? I tried to postponed in this way but am not sure if its true BEGIN IF rising_edge(clock) THEN i:=i+1;  reg1 <= ram1(i); reg2<=reg1; reg3<=reg2; q1<=reg3;

[Altera_Forum]

I highly suggest reading how memory works. You can only access 1 address per clock cycle. So if you really want to access 3 elements to add them, you will have to read them out over 3 clock cycles. You could pipeline the design to do the adds to minimise total latency. 

 I highly suggest using the megawizard ram, as this would become obvious.

[Altera_Forum]

--- Quote Start ---  I highly suggest reading how memory works. You can only access 1 address per clock cycle. So if you really want to access 3 elements to add them, you will have to read them out over 3 clock cycles. You could pipeline the design to do the adds to minimise total latency.  I highly suggest using the megawizard ram, as this would become obvious.  --- Quote End ---    When I create a wizard I don't see how to connect it with my vhdl code in Pedroni book or in the document you sent me.  Also, I wonder if this way of reading in three clock cycles is efficient way  IF rising_edge(clock) THEN i:=i+1;  reg1 <= ram1(i); reg2<=reg1; reg3<=reg2; q1<=reg3;   Or you suggest me better one? Thanks alot

[Altera_Forum]

Your code still suggests you think you're writing software. You are not. You need to understand how the hardware works before you should be writing the code - hence why I suggest drawing a diagram. 

I suggest reading how the ram works from here:  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram.pdf

[Altera_Forum]

--- Quote Start ---  Your code still suggests you think you're writing software. You are not. You need to understand how the hardware works before you should be writing the code - hence why I suggest drawing a diagram. I suggest reading how the ram works from here:  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram.pdf  --- Quote End ---    Ok. I will .  Thank you.