No ouput for Modelsim DDR SDRAM Simulation

[Altera_Forum]

Dear all, 

 In my modelsim simulation of DDR SDRAM write operation, I observed pulse in "local_write_request", "local_burstbegin", and changes in "local_address", "local_wdata", however, I didn't see the ouput from memory, nothing changed on "mem_ras_n", "mem_cas_n" and "men_we_n", (always keep high) and no sigal out from "mem_dq", "mem_dqs" too (always high Z). and no "mem_clk" signal either  Anyone experiences similar problems and how to solve them?  The testbench was generated by SOPC, I added my signals to the Avalon Master template, and did modelsim simulations. The SOPC builder generated altera memory model "altmemddr_test_component.v' to simulate access to the DDR SDRAM memory.  I built a SOPC to control a DDR SDRAM HP controller with a Avalon Memory-Mapped Master Template (http://www.altera.com/support/examples/nios2/exm-avalon-mm.html) (http://www.altera.com/support/examples/nios2/exm-avalon-mm.html%29), without Nios II cpu.  The simulated memory is the DDR SDRAM on cyclone starter kit.

[Altera_Forum]

I was wondering if you had solved your problem with Modelsim, and if so, what did you do to fix it. I seem to be experiencing a similar problem. I'm seeing local interface reponses but nothing between the DDR controller and memory. 

 Thanks.

[Altera_Forum]

Yes, I solved this problem.  

 It was a long time ago. From my memory, you need to set the simulation time very long, >80 us? and you see the DDR controller and memory activity after a long time, especially if you set calibration in the DDR controller, it will take a long time to do calibration or other process before memory access.  Hope it helps.    --- Quote Start ---  I was wondering if you had solved your problem with Modelsim, and if so, what did you do to fix it. I seem to be experiencing a similar problem. I'm seeing local interface reponses but nothing between the DDR controller and memory.   Thanks.  --- Quote End ---  

[Altera_Forum]

Thank you, that was the problem.