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Honored Contributor I

Not Setting Up Correctly Master to Slave Component Under ModelSIM

I am currently attempting to test a custom IP core with Altera's Avalon Master BFM. However, I am having trouble seeing a proper response from the master component to the slave component.  


I have previously attempted to create a Qsys system where I connected the Avalon Master BFM with the custom IP core acting as slave, but I was never able to successfully generate the HDL files for synthesis or simulation in VHDL.  

Because of this, I decided to manually instantiate all port signals for the master and the custom IP core individually and make the proper connections under my testbench VHDL code.  


I then attempted to simulate the connection using ModelSIM and I can see my signals appear on the waveform window, yet I do not see the right response being made by the custom IP core. 


For this setup, I have attempted to utilize already pre-existing VHDL code as provided from this Avalon Master and Slave BFM example here:

From the example, commands are made to burst read, burst write, and then read and write with no-burst. Based on the initial setup, random addresses and data values are being read or written by the master. I have made changes to the VHDL code saved under test_program.vhd and test_program_pkg.vhd in order for me to specify which address and which data I wish to read or write, as well as the amount of burstcount. 


So far, the changes I made to these files seems to have done exactly as I wanted it when viewing under the waveform window. However, under ModelSIM, messages keep appearing stating "Error: wrong burstcount. Error wrong read data. Note: Queue is empty." These message keep appearing at every increment during simulation, but the simulation successfully runs the amount of time I specified.  


If anyone has any advice on how to properly connect a custom IP core with an Avalon Master BFM file, as referenced from the previous link, or know of another method of setting up my system, I would greatly appreciate it.
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Honored Contributor I

The easiest thing to do is generate a testbench system directly in Qsys. Create a new .qsys file that consists of just your custom IP, and export all the interfaces. Then, from the Generate menu, select to generate a testbench system with the Standard option. This will automatically create a new system with all the appropriate BFMs attached to your component and configured based on how your component is set up. This also generates simulation setup scripts (msim_setup.tcl, I believe it's called). See this online training for details: