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Note on CvP Tutorial for V-Series (Linux)

Hello, my post is not a question, but a comment on some of the experiences I have had trying to set up my Cyclone V GT Dev Board. I hope that this will save anyone doing similar work some time.

 

I began my work on a desktop with a fresh installation of Ubuntu 16.04, installed Quartus Prime 18.0, etc. with no issues. I had some experience with FPGAs before, but I still found it difficult to use the CvP tutorial Altera has for the V-series because of crucial missing information.

 

Some googling fixes this issue, so it is not my main concern, but I will summarize here anyway because it is relevant.

 

1.) There is mention of setting the MSEL pins for Stratix FPGAs, but no mention of Cyclone or Arria or where to find the appropriate MSEL settings. You are forced to infer from evidence (if you don't have prior experience) that you must set the MSEL pins for Active Serial. I suggest searching for "MSEL" in the reference manual for your board. I also found the handbook for all Cyclone V devices useful because it has a table that describes the MSEL Settings.

 

2.) If the board has a MAX V, there is a .pof you must load into the MAX V before CvP will function properly. Again, no reference to this in the tutorial. Here's the link to the .pof:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

 

 

 

 

Okay, with that out of the way, here is my main concern. There is a Jungo driver that is included in any Quartus installation that is located at <PATH>/intelFPGA/<VERSION>/quartus/drivers/wdrvr/linux64/

that is pointed to by multiple tutorials. I tried to use it when I needed to write the core image to my FPGA.

 

However, when I ran this Jungo Installation script, it failed to inform me that the driver does not support kernel versions beyond 2.6.x

This version of the kernel has not been maintained in over 7 years.

 

This driver is included even the most recent release of Quartus Prime, but no where outside the installation script code itself is there any reference to the fact that it won't install on kernel versions beyond 2.6.x (including all Altera/intelFPGA documents I've read).

 

This was a source of confusion for me and undoubtedly other users who were following these instructions, especially due to the fact that the installation script failed to report the real error until I recompiled a different version of the kernel. (Again, the one I started with was fresh from the disk and I did make sure I had the kernel headers when debugging)

 

At the very least, I would have expected a README in the directory with the driver installation scripts.

 

These are two of the documents that include instructions to install this Jungo driver in Linux (but fail to mention the kernel version issue):

https://www.intel.com/content/www/us/en/programmable/documentation/nik1412546950394.html#nik14125469...

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_cvp.pdf

 

It's not like these tutorials are ancient and rarely used anymore. The fact that this driver is pointed to without mentioning any of the alternatives is an issue.

 

 

What I ended up doing was using the open source driver located at: https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/devic...

 

This page should be pointed to more often because there was no reference to it, despite the great utility it ended up providing me.

 

 

I hope someone finds this information useful.

Thank you for your patience and have a wonderful evening.

 

Best Regards, Alex

 

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