Novice: TimeQuest analysis

[Altera_Forum]

Hi, 

  I have a pretty basic question that I hope I am asking in the right place please ......   I am using a very old CPLD (a MAX7000) to do the glue logic for a Z80 computer that I have built. I have been struggling a little with the timing and understanding the various constraints that I need to use. I was getting a load of errors in the timing analysis (although the completed design appeared to work), so I have stripped out the majority of the application and want to start adding stuff back with a better understanding of how the timings are working and the relationships between the signals.   To that end, I have just left this "circuit", it takes the oscillator input and uses a couple of LPM_counter blocks to generate lower frequency clocks that can be selected to drive the CPU (the frequency selection is current cut from the application, so the lower frequency clocks just exist as internal CPLD signals and on output pins at this point). (First attachment)    The .SDC clock entries are :-   create_clock -name {Oscillator} -period 31.250 -waveform { 0.000 15.625 } [get_ports {clock}]  (This is used to generate a number of sub-clocks, one of which needs to be further divided to produce a 4/13 clock signal which is independent of the CPU speed).    create_generated_clock -name {Gen4MHz} -source [get_ports {clock}] -divide_by 8 -master_clock {Oscillator} [get_registers {lpm_counter0:Clock_Divider|lpm_counter:LPM_COUNTER_component|dffs[2]}]     TimeQuest reports some paths between the input clock and the generated clock (as is to be expected), but are these really of interest? (Second attachment)     The oscillator provides the "master" clock source, but is the relationship between the master and derived clocks of any importance here?   Various help documents talk about declaring "false paths" which are not significant in the application, so in this example, what do I need to do, constraint wise, to setup the relationship between these signals?   Do I need to, or indeed should I, :-  •Ignore these paths (will they effect any subsequent blocks, e.g., if I use the generated clock to do some logic that will execute at the same frequency as the CPU, will subsequent timing analysis have a problem?) •Declare any false paths? •Do something else?   To my mind, any delay between the two clock is not important, as long as it is consistent.  Obviously, I am a bit of a novice here, so any help would be much appreciated -be gentle :-)  Regards Dave

[Altera_Forum]

Using a combinatorial signal like q[2] as a clock is a bad practice. TQ can hardly analyze it properly and it could lead to problems with counter2. 

The correct solution would be using the global clock for both counters and use q[2] as a clock enable signal for counter2.