On-Chip FIFO crashes FPGA

[Altera_Forum]

I'm using the DE2 board with a NIOS II system. I have on-chip RAM and FIFO and a PS/2 controller attached. The FIFO is single clocked, input and output Avalon MM. I have to write the code for the NIOS II in assembly, as per class instructions. When I try to either read or write from the FIFO, the entire system freezes, and I have to restart both the Altera Monitor Program and the DE2 board. When I look at the memory location that the FIFO registers and in/out ports should occupy, I see question marks, instead of actual data. I built the system using SOPC builder. The in port occupies address 0x4000, the out port 0x4004, and the registers 0x4020 - 0x403f. The fifo clock is the same clock that the NIOS II runs on. Am I missing something programatically or is the system incorrectly build? 

 movia r2, KEY_INPUT movia r3, 0x10 stw r3,(r2)  where KEY_INPUT = 0x4000  This is the instruction that always causes the NIOS II to crash on me.

[Altera_Forum]

--- Quote Start ---  I'm using the DE2 board with a NIOS II system. I have on-chip RAM and FIFO and a PS/2 controller attached. The FIFO is single clocked, input and output Avalon MM. I have to write the code for the NIOS II in assembly, as per class instructions. When I try to either read or write from the FIFO, the entire system freezes, and I have to restart both the Altera Monitor Program and the DE2 board. When I look at the memory location that the FIFO registers and in/out ports should occupy, I see question marks, instead of actual data. I built the system using SOPC builder. The in port occupies address 0x4000, the out port 0x4004, and the registers 0x4020 - 0x403f. The fifo clock is the same clock that the NIOS II runs on. Am I missing something programatically or is the system incorrectly build?  --- Quote End ---     - It sounds like the waitrequest output of the FIFO is getting set and not clearing causing the system to wait forever...just a first guess - Is this a FIFO that you wrote or a proven working design? - Did you run the design on a simulator? If not, you should. It shouldn't take long to create the failure condition since it is simply writing to a single address   Kevin Jennigns

[Altera_Forum]

Kevin, 

 The design is the On-Chip FIFO core that comes with Quartus. Im building a small system in SOPC builder. I looked at the C api and tried to copy that, however, when I try to write to any of the control registers, the registers do not take any value, nor do they have any value. They always appear in the Monitor Program Memory Viewer as question marks, where all the other memory components that I've implemented contain data, whether it is zero's or sets of FF.  Thanks, Max Gardner

[Altera_Forum]

I found the error. SOPC Builder and Quartus II failed to build an initilization file for the memory components. Using the memory initilization file for the on chip RAM allowed for me to be able to push and pull data from the FIFO.