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On-Chip Lookup Sensitivity Processing on Stratix10, Arria 10

stjense
Novice
228 Views

I'm wondering if anyone has had more luck than me in getting On-Chip Lookup Sensitivity Processing working (shown in Figure 1 here).

My understanding of the system is that the user uses the fault injection debugger (FID) to inject a fault in the design. Because CRC’s are being checked, an error appears in the error message register (EMR) IP core. The Advanced SEU Detection (ASD) IP core unloads the error message, and then queries the sensitivity map header (SMH) file to find out what the criticality was of the logic that was hit (a number from 1 to 16). This number is run through user logic that takes some action based on the sensitivity of the logic.

Now, I have some questions.

  • This flow will not work on the Stratix 10 because the ASD IP core is not available for that device, according to the ASD IP core user guide. Is this true?
  • This flow will not work on the Stratix 10 because the EMR IP core is not available for that device, according to the EMR IP Core user guide. Is this true?
  • The ASD IP core user guide states that in order to generate an SMH file, you simply navigate to the device and pin options dialog box and turn on Generate SEU sensitivity map. I have tried this on the following licensed versions on both Arria 10 and Stratix 10 and the box is always greyed out. Is there something I'm missing?
    • 21.1 Pro
    • 20.1.1 Standard
    • 19.3 Pro
    • 16.0 Standard
  • Is there any example design where on-chip lookup sensitivity processing is in place and functional?

Thank you for sharing your wisdom, FPGA community!

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1 Solution
stjense
Novice
100 Views

Ok, it looks like the answer here is that you need FEATUREs in your license file in order to do the sensitivity processing. In the end I contacted the sales department, let them know what I wanted to do, and then they sent me a new license that had more FEATUREs in it.

 

Once you know this is the issue, you can actually see it in one of the user guides. There wasn't anything about it in the Advanced SEU Detecetion IP core guide, nothing in the Error Message Register Unloader IP core guide. However, there's a line in the Fault Injection IP core guide that says,

"The following hardware and software is required to use the Fault Injection Debugger: 

  • FEATURE line in your Intel FPGA license that enables the Fault Injection IP core. For more information, contact your local Intel FPGA sales representative.
  • ...
  • (Optional) FEATURE line in your Intel FPGA license that enables the Advanced SEU Detection IP core."

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11 Replies
YuanLi_S_Intel
Employee
215 Views

Hi,


For Stratix 10, you might need to checkout the document below. It has the IP as well but it is not the same with other devices.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-seu.pd...


Regards,

Bruce


stjense
Novice
209 Views

Bruce,

 

Thank you for pointing me that direction. I've looked at that document when trying to get the system working on the Stratix 10, but found that the Quartus Prime software wouldn't let me put in certain IP (i.e. the EMR register) into the design. It looks like the IP documentation contradicts itself in that regard. The Stratix 10 SEU mitigation user guide states that I should be able to use it, but the user guides for the individual IP state that the Stratix 10 is not supported. And my experience points to the fact that the Stratix 10 is not supported for several IP blocks.

 

Another issue I ran into was that in that user guide you referenced, it talks about using an SMH file. However, that option does not exist when I navigate to the Device and Pin Options menu. It's not that the checkbox isn't clickable, but doesn't exist altogether.

 

Do you by chance have an example design with this flow working that I could use to start from? Or do you have any answers to my questions asked above?

YuanLi_S_Intel
Employee
200 Views

Well you mentioned that it works previously, any idea what was the version?


Also, have you tested on different host PC?


YuanLi_S_Intel
Employee
199 Views

i am able to see the option with Stratix 10 opened on v21.1 Quartus Pro. Any idea which version you are using?


stjense
Novice
192 Views

Bruce,

 

I have never been able to get this flow to work. By that, I mean that I've never been able to inject faults with the FID and recover from the error via the ASD reading the SMH file and interpreting the error. I have tried on 21.1 Pro, 20.1.1 Standard, 19.3 Pro, and 16.0 Standard with no luck. You say that you can se the option on Stratix 10 with 21.1 Pro, right? Could you send me your design?

 

Thank you!

stjense
Novice
190 Views

Are there any specific lines I need in my QSF file that I don't have? Is there some secondary tool I need to download?

 

I'm at a loss as to why it's working for you and not for me, so I'd like to replicate your setup as much as I can so that I can produce the same result.

YuanLi_S_Intel
Employee
180 Views

Could you try with a empty design? I dont do any setting, just create a new design in new folder and i can see the option selectable.


stjense
Novice
171 Views

I created six different blank designs. In each scenario I followed the steps below:

  • Open the Quartus Software
  • Create a  new project
  • Select the part from the table below
  • Did not add any source files
  • Finish creating the project
  • Return to Assignments > Device > Device and Pin Options > Error Detection CRC
  • Record the options I have there

The table below shows the results.

Quartus Version Part Result
Quartus Prime 16.0 Standard (licensed) 10AXS2F45I1SG Generate SMH file was greyed out (not selectable). The other options were enable error detection CRC_ERROR pin, enable open drain on CRC_ERROR pin, enable internal scrubbing, divide error check frequency by.
Quartus Prime 19.3 Pro (Licensed) 10AXS2F45I1SG Generate SMH file was not an option. The options were enable error detection CRC_ERROR pin, enable open drain on CRC_ERROR pin, enable internal scrubbing, divide error check frequency by.
Quartus Prime 19.3 Pro (Licensed) 1SG280LU3F50E3XG Generate SMH file was not an option. The options were enable error detection check, minimum SEU interval, enable internal scrubbing.
Quartus Prime 20.1.1 Standard (Licensed) 10AXS2F45I1SG Generate SMH file was greyed out (not selectable). The other options were enable error detection CRC_ERROR pin, enable open drain on CRC_ERROR pin, enable internal scrubbing, divide error check frequency by.
Quartus Prime 21.1 Pro (Licensed) 10AXS2F45I1SG Generate SMH file was not an option. The options were enable error detection CRC_ERROR pin, enable open drain on CRC_ERROR pin, enable internal scrubbing, divide error check frequency by.
Quartus Prime 21.1 Pro (Licensed) 1SG280LU3F50E3XG Generate SMH file was not an option. The options were enable error detection check, minimum SEU interval, enable internal scrubbing.

 

These are all of the configurations I have tried. As you can see, I've tried on the Arria 10 and the Stratix 10 on many different versions (pro and standard) all of which were licensed. My license is a Quartus Prime Pro Fixed that expires in April 2022. 

 

Any other thoughts? Is it possible that this feature is only supported on internal versions of Intel FPGA Quartus Prime? And the version that is released to the public does not have this capability?

stjense
Novice
135 Views

Bruce,

 

I hope I haven't lost you. I have tried with empty designs on many different configurations and cannot get the tools to generate an SMH file for me.

 

Is it possible that I need features added to my license in order to run this flow? If so, which ones?

 

Thank you.

stjense
Novice
101 Views

Ok, it looks like the answer here is that you need FEATUREs in your license file in order to do the sensitivity processing. In the end I contacted the sales department, let them know what I wanted to do, and then they sent me a new license that had more FEATUREs in it.

 

Once you know this is the issue, you can actually see it in one of the user guides. There wasn't anything about it in the Advanced SEU Detecetion IP core guide, nothing in the Error Message Register Unloader IP core guide. However, there's a line in the Fault Injection IP core guide that says,

"The following hardware and software is required to use the Fault Injection Debugger: 

  • FEATURE line in your Intel FPGA license that enables the Fault Injection IP core. For more information, contact your local Intel FPGA sales representative.
  • ...
  • (Optional) FEATURE line in your Intel FPGA license that enables the Advanced SEU Detection IP core."
YuanLi_S_Intel
Employee
114 Views

Hi,


Can you check if your quartus licensed is specifying the correct license? I am able to see the option grey out when the license is not available.


Thank You.




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