Re: One clock output pulse from debounce logic

Altera_Forum · ‎02-09-2011

I can't figure it out how to get a 1 clock output pulse from debounce logic ? I always get a pulse that is longer then my main clock's 50 MHZ period (20 ns). The debounce registers are updated every 10 ms and I don't have an idea how to "convert" this back into a pulse of 20 ns ...

library ieee;
use ieee.std_logic_1164.all;
entity debounce_03 is
    port (clk,reset: in std_logic; -- clk frequency = 50Mhz
            pb: in std_logic;
            pb_debounced: out std_logic ;
            single_pulse_output : out std_logic
            );
end entity debounce_03;
architecture rtl of debounce_03 is
    signal count500000 : integer range 0 to 499999;
    signal clk_100Hz: std_logic;
    signal pb_sampled: std_logic;
    signal pb_sampled2: std_logic;
    signal pb_latched: std_logic; -- extra latch dus
    signal pb_dblong: std_logic;
begin
div_100Hz: process(clk,reset) is
begin
    if reset ='1' then
        clk_100Hz <= '0';
        count500000 <= 0;
    elsif rising_edge(clk) then
        if count500000 = 499999 then
            count500000 <= 0;
            clk_100Hz <='1';
        else
            count500000 <= count500000 + 1;
            clk_100Hz <='0';
        end if;
    end if;
end process div_100Hz;
debounce_pb: process(clk) is
begin
    if rising_edge(clk) then
        if clk_100Hz ='1' then
            if pb_latched = pb_sampled then
                pb_debounced <= pb_latched ;
            
            end if ;
            pb_sampled <= pb_latched;
            pb_latched <= NOT pb;
        end if;
    end if;
end process debounce_pb;
        
tick : process(clk) is
begin
    if rising_edge(clk_100Hz) then
            single_pulse_output  <= pb_latched AND NOT pb_sampled ;
    end if ;
end process tick;            
end architecture rtl;

Altera_Forum · ‎02-09-2011

I ditched VHDL long ago so I'll describe this at a high level.

Build a down counter that counts down while the signal you are debouncing is in it's "active" state. Any time the signal bounces back to the non active state then you reset the counter to it's initial value. If the counter hits 0 detect this and drive a signal called "detected" high. Wire "detected" into a rising edge detector to create a one cycle pulse.

In case you haven't built a rising edge detector what you would do is register "detected" and call it ... "detected_d1". Then you create the one cycle pulse like this:

strobe = detected AND (NOT detected_d1) <--- however you write this in VHDL....

If you draw the waveform of this logic you'll see how it works.

So coding it this way you shouldn't even need a statemachine; however, you can still use one to implement the downcounter.

Altera_Forum · ‎02-10-2011

Ok it works with a counter , so my FIFO finally works !! :D (I use this pulse to write into a FIFO ....