Open drain pin assignment

[Altera_Forum]

Does anyone know how to make an output pin open drain? I made an open drain assignment to an output pin in the assignment editor, but Quartus ignores it.

[Altera_Forum]

You need to instantiate an open drain primitive just before the pin. For some reason Quartus wont do this for you when you use the assignment editor to make an open drain assignment.

[Altera_Forum]

If the port is always driven '0', and other logic only feeds the output enable, then Quartus should automatically convert the output to an open-drain, without you having to make an assignment.

[Altera_Forum]

and we must use the open drain primitive for each pin ? 

module opndrn (in, out);   input in;   output out;      bufif0 (out, in, in);  endmodule

[Altera_Forum]

I don't think you have to go that low. Just saying 

 someoutput = 1'b0 ? drivenlow ! 1'bz;  should do the trick - but my Verilog is very, very rusty. I do not know how to expand this to a bus in Verilog, but in VHDL it would read something like  for i in bus'RANGE loop  if bus(i) = '0' then  buspin(i) <= '0';  else  buspin(i) <= 'Z';  end if; end loop;  Does that answer your question?  Best regards,   Ben

[Altera_Forum]

There is no setting to force Quartus to make an open-drain pin. However, as btwjinst said, Quartus can convert a tristate buffer with a '0' input to an open-drain automatically, if you enable "Auto Open-Drain Pins" and "Perform WYSIWYG Primitive Resynthesis" under Quartus Settings.

[Altera_Forum]

In Quartus II assignment editor, you can set the pin as auto open drain. 

You can also set it in *.qsf file: set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to XXXXX