Output enables MAX3000 in QII 9.0

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Output enables MAX3000 in QII 9.0

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Hi,

I will compile my old project in newer version QII 9.0 and I have problem with fitter with next message: "Error: Design requires 8 output enable signals, but the device can contain only 6 output enable signals".

In older QII 6.0 was not a problem.

How to reduce design output enable signals manually?

Help me, please.

Thank You

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