Overpowering core of Low Power FPGA (1.2V instead of 1.0V)

[Altera_Forum]

I am using both EP4CE10F17C8LN with a 1.0V core voltage and the EP4CE10F17C8N with its core at 1.2V 

 I wonder if there is any risk in powering the 8LN's core at 1.2V - The absolute maximum rating is at 1.8V  I expect it to only make the timings better than predicted for this FPGA, but I'd like to know for sure.  Thanks

[Altera_Forum]

It is the same die that passed different tests, so you shouldn't have any risk running it at 1.2V. 

As you say the timing will be faster, but as a result you could have a problem with hold requirements. The fast 1V model is probably slower than the fast 1V2 model, so you may have hold violations. I would recommend to run timequest with a 1V2 device model to be sure.

[Altera_Forum]

Any specific reason why you would like to do that by the way? The EP4CE10F17C8LN is probably a die that has characteristics very close to a EP4CE10F17C7N, and IIRC they are at the same price. Other than logistics there shouldn't be any reason to want to run a 1V0 device at 1V2.

[Altera_Forum]

Strictly spoken, it's not said in the datasheet that the 1.0V "L" types can be used at 1.2V, although I share the respective guesses.